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An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting andScaling

Xuan-Lun Huang and Jiun-Lang HuangGraduate Institute of Electronics Engineering

Department of Electrical Engineering National Taiwan University, Taipei 10617, Taiwan

Abstract This paper presents a loopback methodology forstatic linearity testing of an ADC/DAC pair; the key idea isto raise the effective ADC and DAC resolution by scaling theDAC output. First, during ADC testing, we scale down theDAC output to achieve the needed test stimulus resolution andadjust the DAC output offset to cover the ADC full-scale range.Then, for DAC testing, we raise the effective ADC resolution byscaling up the DAC output. Both simulation and measurement

results are presented to validate the proposed technique. Keywords -mixed-signal testing, loopback testing, design-for-

test, ADC/DAC testing, segmented current-steering DAC.

I. INTRODUCTION

Analog-to-digital and digital-to-analog data converters(ADCs and DACs) are essential building blocks in moderncommunication and multimedia devices. To catch up withthe rapid data volume growth, the development of high-speedand high-resolution data conversion techniques has neverstopped. While meeting the data bandwidth requirement,these high-end converters also pose serious challenges to

manufacturing testing because data converter testing mostlyconsists of specication-based functional testing.

Since mixed-signal System-on-Chips (SoCs) often containboth ADC and DAC, the loopback testing methodology thatdirects the DAC output to the ADC input (through some ana-log signal processing path) so that they can test each otherbecomes a promising solution to ATE (automatic test equip-ment) cost reduction. While attractive, the loopback testingmethodology is limited by the achievable test resolution andthe potential fault masking problem. Over the years, severaltechniques have been developed to address these issues.In [1], the authors presented a loopback testing scheme thatutilizes spectral predictors and a simple analog lter on an

external load board to estimate the dynamic performance of data converters. Based on [1], Park et al. developed a parallelloopback testing approach in [2]. These methods requireintensive computation to derive the dynamic performanceparameters. For static linearity testing, [3] proposed to rstestimate the ADC linearity based on the noise distribution.Then, the characterized ADC is employed to test the DAC.

This work was partially supported by the National Science Council of Taiwan, R.O.C., under Grant No. NSC 98-2220-E-002-006-.

[4] proposed another noise-based loopback testing scheme.It characterizes the DAC performance with the spectralprediction technique [1], utilizes a digital equalizer to com-pensate for the DAC nonlinearity, and measures the ADCperformance by the traditional histogram method. To ensuretest accuracy, these noise-based approaches demand a largenumber of samples; this elongates the test time.

In this paper, we propose a static ADC/DAC loopback testing methodology for cases that utilize the segmentedcurrent-steering DAC (SCS DAC). The key idea is to raisethe effective ADC and DAC resolution by properly scalingthe current-steering DAC output. During ADC testing, theSCS DAC output is scaled down and offset by a set of DC values so as to produce the ADC histogram testingstimulus. As for DAC testing, the effective ADC resolutionis improved by scaling up the DAC output. Then, the ADC isutilized to test one current source in the SCS DAC at a time.From the results, the DAC I/O (input/output) transfer curvecan be constructed assuming that the current summation isideal.

The contributions and advantages of the proposed loop-back testing methodology are as follows.

1) We propose to achieve the needed test resolution forstatic ADC and DAC testing, including DNL (differ-ential non-linearity) and INL (integral non-linearity),by simply scaling the DAC output. For SCS DAC, thiscan be easily realized by adjusting the load resistancevalue.

2) The proposed technique is robust. The scaling factorsand the set of offset voltages need not be very accurate.

Both simulation and measurements on off-the-shelf ADC/DAC show that the proposed technique achievesalmost identical results to the conventional method. Thelimitation is that the DAC must be of the segmentedcurrent-steering architecture.

The rest of this paper is organized as follows. In Sec-tion II, we briey introduce the basic structure and operationprinciple of the SCS DAC. In Section III, we illustrate theproposed technique in detail. Simulation and experimentalresults are given in Section IV and Section V respectively,and we conclude this paper in Section VI.

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Figure 1. A 6-bit segmented current-steering (SCS) DAC.

I I . S EGMENTED C URRENT -S TEERING DAC

The segmented current-steering (SCS) DAC is very pop-ular for high-performance applications. Internally, an N -bit SCS DAC is divided into two segments: the unary-weighted segment for the N MS B more signicant bits andthe binary-weighted segment for the N LSB less signicantbits. (N = N MS B + N LSB .) The SCS DAC architecturecombines the advantages of the unary and binary-weightedarchitecturethe former relieves the output glitch problem;the latter reduces the circuit size.

Take the 6-bit SCS DAC in Fig. 1 for example. It hasN MS B = 2 and N LSB = 4 ; thus, it uses 2N MSB 1 =3 unary-weighted (I 6 , I 5 , and I 4 ) and 4 binary-weighted(I 3 , I 2 , I 1 , and I 0 ) current sources that are related by

I i =2N LSB I 0 if i > 32i I 0 otherwise (1)

While one can use D 3 to D 0 to directly control the binary-

weighted current sources I 3

to I 0

, a binary-to-thermometerdecoder is needed to generate the control signals to theunary-weighted current sources (I 6 , I 5 , and I 4 ) from D 4and D 3 . The total output current (I DAC ) is directedto the load resister (R L ) to produce the output voltage(V DAC = I DAC R L ).

It is worth noting that one can control the SCS DACsfull scale range (FSR) by adjusting R L ; this forms the basisof the proposed ADC/DAC loopback testing technique.

III . T HE PROPOSED ADC/DAC L OOPBACK T ESTINGT ECHNIQUE

The proposed technique takes advantage of the fact that

one can adjust the SCS DACs load resistance to changeits full scale range (FSR). When testing ADC, we use theSCS DAC to generate the ramp stimulus and derive theADC non-linearity via the linear histogram approach. Theproposed technique achieves the required ramp resolution byscaling down the DAC FSR; this raises the effective DACresolution because there will be more DAC output voltagesthat fall inside each ADC code step. To compensate for thereduced DAC FSR, we add a set of offset voltages to theDAC generated ramps so as to cover the ADC FSR. As for

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Figure 3. The gain control block.

DAC testing, we use the ADC to test one current sourceat a time by measuring the produced output voltage. Notethat this requires modication to the binary-to-thermometerdecoder. To achieve the required measurement resolution,the proposed technique scales up the DAC output.

In the following, we will describe the hardware that sup-ports the proposed loopback methodology and the loopback testing ow. For ease of illustration, we make the following

assumptions. The ADC and DAC have the same FSR. The ADC and DAC have the same number of bits.

Note that, in general, one can apply the proposed techniqueto other cases easily.

A. The loopback testing architecture

Fig. 2 depicts the proposed loopback testing architecture.The DAC under test is a current-output SCS DAC; it has atest enable signal ( T E ) which allows turning on each currentsource individually during DAC testing. The ADC undertest, on the other hand, can be of any architecture and needs

no modication.The loopback path consists of the gain control andoffset control blocks. The gain control block is a simpleresistor network as shown in Fig. 3 where R DAC > R L >R ADC ; it generates scaled DAC outputs. During normaloperation, 1 is closed; this directs the DAC output currentI DAC to the normal load resistor R L and produces outputvoltage V DAC = I DAC R L . During ADC testing, 2 isclosed and R ADC is used to scale down V DAC ; during DACtesting, 3 is closed and R DAC is used to scale up V DAC .

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Figure 5. Covering ADC FSR with multiple segments.

The offset control block (Fig. 4) adds DC offset V OS tothe DAC output. Using a set of properly selected DC offsetvalues, this allows the down-scaled DAC outputs to coverthe ADCs FSR. As shown in Fig. 5, without DC offset, theDAC generated ramp, SEG 1 , only covers a small portionof the ADC FSR. By using multiple ramps with differentoffset voltages, the ADC FSR can be covered. Note thatthese DC offset voltages do not have to be very accurate aslong as the ADC FSR is fully covered and there is sufcientoverlap between adjacent segments to compensate for noiseand offset voltage deviations. In Fig. 4, the offset voltage isfrom the DAC and stored in the sample-and-hold (S/H) unit.In practice, one may use an external DC source if readilyavailable.

B. ADC testing

Fig. 6 depicts the proposed ADC testing ow. First, thegain control block (Fig. 3) selects R ADC which is timessmaller than R L ; this scales down the DAC output by .Then, the ow enters the partial histogram collection loop.In the i-th iteration, the offset voltage V OS i is applied tothe offset control block. Then, we sweep the DAC inputcode and collect the corresponding ADC code hits, i.e., the

number of times each code appears. Note that the DACoutput only covers the range from V OS i to V OS i + F SR ,denoted by SE G i ; thus, the histogram obtained in iterationi is a partial histogram, denoted by Hist i , that charac-terizes the ADC behavior within input range SE G i . Thenoise, if present, causes the ADC output code to deviatefrom its ideal value; this affects the accuracy of obtainedpartial histograms, especially for the codes that are closeto the segment boundaries. Furthermore, the offset voltagesmay deviate from their specied values. To tolerate these,

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Clearly, V overlap must exceed V OS dev to tolerate the offsetvoltage deviations. The reason of adding the 6 noise term isaccording to the partial histogram truncation process whichremoves 2 codes from both ends of each partial histogram.Finally, the additional 1 LSB term ensures that one canderive the full histogram by combining the truncated partialhistograms.

C. DAC testing

The proposed loopback testing technique utilizes the ADCto test the DAC by measuring the output voltage produced byeach current source. Fig. 7 illustrates the DAC testing ow.First, the gain control block selects R DAC which is timeslarger than R L ; this scales up the DAC output by . Then,the ow enters the current source testing loop. Each time,exactly one current source I i is connected to R DAC . Thecorresponding scaled output voltage V DAC i = I i R DAC ismeasured by the ADC and stored. For an N -bit SCS DACthat has N MS B unary-weighted more signicant bits andN LSB binary-weighted less signicant bits, this loop repeatsN LSB + 2 N MSB 1 times. Once all the current sources aremeasured, one can construct the full DAC I/O transfer curve

(assuming that the summation is ideal) from which the DACDNL and INL can be derived.1) Choice of : Intuitively, by increasing , the relative

quantization error caused by the ADC becomes smaller;however, is limited by the ADC FSR. When the largestcurrent source, i.e., a unary-weighted one, is tested, the re-sulting output voltage must be within ADC FSR. Accordingto (1), we have

2N LSB I 0 R DAC F SR (4)

Since the maximum DAC output covers the ADC FSR whenloaded with R L , we have

2N 1 I 0 R L = F SR (5)

From (4) and (5) and R DAC = R L , we have

2N

12N LSB 2N MSB (6)

Note that (6) also implies that the achievable test accuracyof this DAC testing scheme is limited by the segmentedcurrent-steering DAC architecture.

2) DAC design for testability: To realize the DAC testow, the binary-to-thermometer decoder is re-designed sothat when the T E (test enable) input is high, one can turnon the unary-weighted current source under test by properlysetting the N MSB more signicant bits.

D. Discussions

While we can raise the effective ADC/DAC test resolutionby scaling down/up the DAC output, the achievable testaccuracy is ultimately limited by the non-linearity associatedwith the ADC and DAC.

Let ENOB DAC be the DACs effective number of bits. The effective ADC test resolution is approximatelyENOB DAC +log 2 . If the DAC is highly non-linear, onecan increase to maintain the required test accuracy atthe cost of elongated test time (because more segments areneeded to cover the ADC FSR). The analysis is similar forDAC testing. However, since is upper bounded, the desiredDAC test resolution is not always attainable.

IV. S IMULATION RESULTS

We rst perform numerical simulations to validate theproposed technique. The FSR of the DAC output and theADC input are both 2 V. The ADC under test is a 12-bitone-bit/stage pipelined ADC. In each stage, the capacitormismatch is randomly set to be within 0.3% and the com-parator offset is randomly assigned between -3 and +3 mV.The DAC under test is a 12-bit segmented current-steeringDAC with N MS B = 6 and N LSB = 6 ; the deviation of eachcurrent source is randomly assigned and bounded by 1%.During testing, both scaling factors and are set to sixty.Note that, zero noise is assumed during the simulation todemonstrate the maximum achievable test accuracy.

A. ADC testing simulation results

The ADC is rst tested by a perfect 20-bit DAC. Themeasured INL and DNL are shown in the left-hand side(LHS) plots of Fig. 8; the maximum DNL and INL are2.60 and 3.05 LSB, respectively. Note that these results areconsidered as the ideal values. Then, the proposed ADCloopback testing technique is applied. The measured INLand DNL are shown in the right-hand side (RHS) plots of Fig. 8; the measured maximum DNL and INL are 2.61 and

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Figure 9. The simulated ADC test errors.

3.07 LSB, respectively. From Fig. 8, it is easy to see thatthe INL/DNL values obtained by the proposed technique arealmost identical to the ideal values. Finally, the INL/DNLmeasurement errors are shown in Fig. 9; the errors are allless than 0.06 LSB.

B. DAC testing simulation results

The DAC testing simulation results are shown in Fig. 10.On the LHS of the gure are the actual DNL and INL plotsof the DAC; the peak DNL and INL are -0.62 and -1.92 LSB,respectively. On the RHS of the gure are DNL and INLplots obtained by the proposed technique; the peak DNL andINL are -0.63 and -1.93 LSB, respectively. The measurementerrors are shown in Fig. 9 and are all within 0.04 LSB of the actual values.

V. E XPERIMENTAL R ESULTS

Experiments on commercial ICs are also performed tofurther validate the proposed technique. The ADC undertest is a 10-bit pipelined ADC (ADS825 from TI). On theother hand, the DAC under test is emulated using a 14-bitcurrent-output DAC (THS5671A from TI); it is a 10-bit SCSDAC with N MSB = 6 and N LSB = 4 . The reasons to usean emulated DAC are as follows. First, we are unable tomodify the binary-to-thermometer decoder of commercial

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SCS DACs to realize the DAC test ow. Secondly, thisfacilitates very exible fault injection to the DAC. In theexperiments, each current source in the emulated DAC israndomly perturbed by within 2% of its nominal value. TheADC and DAC have the same FSR of 2 V and are bothoperated at a sampling rate of 100 KHz.

The scaling factor is set to 25, and is set to 60; this isachieved by setting R L , R ADC and R DAC in Fig. 3 to 100, 4 and 6 K , respectively. The offset control circuit isimplemented by an opamp-based adder; the required offsetvoltage is provided by NI DAQ (USB-6259). The noise ismeasured by applying a DC value to the ADC and observethe output code distribution; the measured noise standarddeviation is about 0.25 LSB.

A. ADC testing experimental results

We rst characterize the ADC under test (ADS825) withthe 14-bit DAC (THS5671A). The LHS plots in Fig. 12 showthe measured DNL and INL. The peak DNL and INL valuesare 0.73 and -2.54 LSB, respectively.

The proposed loopback ADC testing technique is thenapplied. Note that (1) the 10-bit DAC is emulated with a14-bit one and is fault-injected, and (2) the offset voltagesare generated by NI DAQ (USB-6259). The measurementresults are shown in RHS plots of Fig. 12. The peak values

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Figure 12. The ADC testing experimental results.

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Figure 13. The ADC testing errors.

of the estimated DNL and INL are 0.80 and -2.53 LSB,which are very close to the actual values.

The estimation errors are shown in Fig. 13; the maximumDNL and INL measurement errors are 0.19 and 0.36 LSB,respectively.

B. DAC testing experimental results

The actual performance of the emulated 10-bit DACunder test is rst measured by NI DAQ which has a 16-bit resolution. The LHS plots of Fig. 14 show the measuredDNL and INL performance; the peak DNL and INL are 0.96and 3.57 LSB, respectively.

As the emulated 10-bit DAC has N MSB = 6 and N LSB =

4, there are a total of 4 + 26

1 = 67 emulated currentsources. The output voltages with respect to each of theemulated current sources (loaded by R DAC ) is digitized bythe 10-bit ADC (TI ADS825). From the measured voltages,the DAC I/O transfer curve is constructed to derive the DNLand INL; the results are shown in the RHS plots of Fig. 14.The peak estimated DNL and INL values are 0.97 and 3.30LSB, respectively. The DAC DNL/INL test errors of theproposed technique are shown in Fig. 15; the peak DNLand INL errors are 0.16 and -0.32 LSB, respectively.

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Figure 15. The DAC testing errors.

VI. C ONCLUSION

This paper presents a low-cost yet efcient static loopback testing technique for an ADC/DAC pair when the DAC is

a segmented current-steering one. The proposed techniqueis a promising solution to SoCs with both ADC and DACdue to its simplicity and low DfT hardware requirement.Experimental results based on commercial ICs show thatvery high test accuracy can be achieved even in the presenceof noise. In the future, we will investigate the potential faultmasking issue and develop techniques to avoid or recognizeits occurrence.

REFERENCES

[1] H. Shin, B. Kim, and J. A. Abraham, Spectral prediction forspecication-based loopback test of embedded mixed-signalcircuits, in VLSI Test Symposium , Apr. 2006, pp. 412417.

[2] J. Park, H. Shin, and J. A. Abraham, Parallel loopback testof mixed-signal circuits, in VLSI Test Symposium , Apr. 2008,pp. 309316.

[3] J.-H. Chun, H.-S. Yu, and J. A. Abraham, An efcient linearitytest for on-chip high speed ADC and DAC using loop-back,in Great Lakes Symposium on VLSI , Apr. 2004, pp. 328331.

[4] H. Shin, J. Park, and J. A. Abraham, A statistical digitalequalizer for loopback-based linearity test of data converters,in Asian Test Symposium , Nov. 2006, pp. 245250.

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