A 60-GHz Efficiency-Enhanced On-Chip Dipole …Performance Comparison 15 2014-10-1 WU Rui, Tokyo Tech Ref. CMOS Process Type of on-chip antenna Freq. Antenna gain Core area This work

A 60-GHz Efficiency-Enhanced On-Chip

Dipole Antenna Using Helium-3 Ion

Implantation Process

Rui Wu, Wei Deng, Shinji Sato, Takuichi

Hirano, Ning Li, Takeshi Inoue, Hitoshi

Sakane, Kenichi Okada, and Akira Matsuzawa

Tokyo Institute of Technology, Japan

1

• 60-GHz Application and CMOS On-Chip Antenna • Conventional Solutions • Proposed On-Chip Antenna using Helium-3 Ion Irradiation • Performance Comparison and Conclusions

Outline

2014-10-1 WU Rui, Tokyo Tech

2 Motivation


1980 1985 1990 1995 2000 2005 2010 2015

101

102

103

104

105

106

WDM

OC-192

2λ 4λ

8λ 32λ

160λ

300Gbps

Ca

pa

cit

y [

Mb

ps

]

OC-48

OC-24

OC-12

OC-3

Wireline

802.11 802.11b 802.11a

802.11g 802.11n

UWB

100 Bluetooth

PHS PDC

Millimeter-Wave

10Mbps

Wireless (PAN～WAN)

10Gbps

Contents

3 60-GHz CMOS On-Chip Antenna


60-GHz TX chip

Chip package

Bonding wire

Metal plate 60-GHz TX chip

Off-chip antenna:

High radiation gain

parasitic components

and loss for connection

Degrade system

performance and

design flexibility

CMOS On-chip antenna:

Much less parasitic and

connection loss

flexible design and

monolithic integration

Poor radiation gain due

to lossy substrate

4 Conventional Solutions (1/2)

• Artificial Magnetic Conductor (AMC)


[1] X.-Y. Bao et al., ITAP 2012

High-Z surface to prevent EM field induced in the lossy substrate Large area for AMC pattern

AM

C p

lan

e

A

A’

Antenna component(Top metal)

AMC plane(Metal 1)

SiO2

Lossy substrate

AA’

5 Conventional Solutions (2/2)

• Proton implantation


[2] K.-T. Chan et al., IEDM 2001

Increase substrate resistivity to prevent induced EM field

High dose amount and process cost

A

Antenna component

(Top metal)

Proton implantation

region

Lossy

sub.

A’

AA’

6 Proposed Gain-Enhanced Antenna


Increase substrate

resistivity (≈103Ω•cm)

Less dose amount

and process cost

Less lateral scattering

and higher reliability

Helium-3 ion irradiation

7 Helium-3 Bombardment Procedure


Set wafer in plate

Max 4

Wafers/Plate

Wafer Chamber

Wafer Transport Equipment

Max 139

Plates/Batch

Auto-Transport Wafers

irradiated one by one

Move plate into

chamber

Vacuum pumping

Ion irradiation

Air pumping

Move plate out of

chamber

Wafer Plate Confidential

8 Measured Resistivity versus Dose


1E+0

1E+1

1E+2

1E+3

1E+4

1E+12 1E+13 1E+14 1E+15

Dose (cm-2)

Resis

tivit

y (

Ω•c

m)

Helium-3

Proton

100

101

102

103

104

1012 1013 1014 1015

[3] N. Li et al., VLSI Technology 2014 [4] L.-S. Lee et al., ITED 2001

N-type substrate

9 Measured Resistivity versus Depth


1E+0

1E+1

1E+2

1E+3

1E+4

1E+5

0 50 100 150 200 250 300 350

Depth (μm)

Resis

tivit

y (

Ω•c

m)

w/ ion irradiation

w/o ion irradiation

100

101

102

103

104

105

10 On-Chip Antenna Configuration


1000 mm

A A’

30 mm

MSL

Dipole antenna element

10 mm

270 mm1

80

mm

2100 mm

21

00

mm

40 mm

SiO2

Si sub.

Al (1 μm)

40 mm 160 mm 320 mm

Ion irradiated region

11 Die Micro-photograph


Dip

ole

an

ten

na e

lem

en

ts

He

liu

m-3

io

n irr

ad

iate

d r

eg

ion

460 μm

12

00

μm

65 nm CMOS technology

12 Measurement Setup


Vector Network Analyzer

Agilent N5247A PNA-X

(10 MHz-67 GHz)

Probe Probe

Chip Tray

h=

4.0

mm

Probe Station Metal Plate

Chip Tray

R=2.5 cm

Chip

Probe Station Metal Plate

13 Measured Antenna Gain


-8

-6

-4

-2

0

57 59 61 63 65 67

w/o ion irradiation

w/ ion irradiation

An

ten

na G

ain

(d

Bi)

Frequency (GHz)

Depth 40μm

Depth 160μm

Depth 320μm

14 Measured S11


-15

-10

-5

0

57 59 61 63 65 67

w/o ion irradiation

w/ ion irradiation

S11

(d

B)

Frequency (GHz)

Depth 40μm

Depth 160μm

Depth 320μm

15 Performance Comparison


Ref. CMOS

Process

Type of on-chip

antenna Freq.

Antenna

gain Core area

This

work 65 nm

Dipole with helium-

3 ion irradiation 60 GHz -2.0 dBi 0.48 mm2

[1] 180 nm Circularly polarized

with AMC 65 GHz -4.4 dBi 3.24 mm2

[5] 180 nm Yagi 60 GHz -10.0 dBi 0.74 mm2*

[6] 90 nm Yagi with AMC 60 GHz -7.2 dBi 1.04 mm2

[7] 65 nm Slot loop 60 GHz -5.0 dBi* 0.64 mm2*

[8]

Post-back-

end-of-line

(10 Ω•cm)

Inverted-F 61 GHz -19.0 dBi 0.20 mm2*

Quasi-Yagi 65 GHz -12.5 dBi 0.59 mm2*

*Estimated from literature

[5] H.-R. Chuang et al., ITED 2011

[1] X.-Y. Bao et al., ITAP 2012

[6] H.-C. Kuo et al., ITMTT 2013

[7] L. Kong et al., ISSCC 2013 [8] Y.-P. Zhang et al., ITED 2005

16 Conclusions


• 60-GHz on-chip dipole antenna with

helium-3 ion implantation technique

• Small dose amount (3x1013 cm-2)

• Average 3-dB gain improvement across

57 GHz~67 GHz

• Peak gain of -2.0 dBi @ 60 GHz

with 0.48 mm2 area

17

Thank you very much for your attention

Q & A


Documents

A 60-GHz Efficiency-Enhanced On-Chip Dipole …Performance Comparison 15 2014-10-1 WU Rui, Tokyo Tech Ref. CMOS Process Type of on-chip antenna Freq. Antenna gain Core area This work