AD Firmware1

8/10/2019 AD Firmware1

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1. Introduction

1.1 PurposeThis document covers the details of firmware design implemented in Virtex-II FPGA of WG-DPEC-1.0board which is used in Digital Closed Loop Fiber Optic Gyro system.

1.2 Scope

The scope of this document covers the design and development efforts involved in Firmware for ClosedLoop DFOG. It covers the following points associated with the intended system, Product perspective,functional description, end users’ perspective, product functions and specifications. It then details designconstraints and assumptions and dependencies.

1.3 List of abbreviations

ACC Accelerometer

ADC Analog to Digital ConverterBRAM Block Random Access MemoryCLB Configurable Logic BlockCLFOG Closed Loop Fiber Optic GyroDAC Digital to Analog ConverterDCM Digital Clock ManagerDFOG Digital approach Fiber Optic GyroDFS Digital Frequency SynthesizerDLL Delay Locked LoopDPEC Digital Phase Estimator CardDSP Digital Signal ProcessorFDD Firmware Design DocumentFF Flip Flop

FIFO First In First OutFOG Fiber Optic GyroFPGA Field Programmable Gate ArrayIIC (I2C) Inter Integrated-circuit CommunicationJTAG Joint Test Action GroupLUT Look Up TableLVDS Low Voltage Differential SignalNA Not ApplicablePC Personal ComputerPINFET P Intrinsic N Field Effect TransistorRAM Random Access MemoryROM Read Only MemoryRCI Research Centre ImaratSLD Super Luminescent DiodeSPI Serial Peripheral InterfaceSRS Specification Requirement SheetTBD To Be DiscussedUART Universal Asynchronous Receiver TransmitterVHDL Very High Speed Integrated Circuit Hardware Descriptive LanguageWG Wavelet Group



1.4 References

• WG-DPEC-1.0 SRS Document

• Technical specification manuals of VIRTEX-II FPGA of Xilinx• Data sheets of on-board components like ADC (ADS8422), DAC (LTC1668)

• Schematic of WG-DPEC-1.0

• Technical reference papers from RCI

1.5 Document Overview

WG-DPEC-1.0 FPGA Firmware Design Document covers the following

• Assumptions and dependencies

• Firmware design constraints

• Technical specifications

• Design description

• Implementation details

• External, internal and user interfaces

• Memory Mapping



2. General Description

2.1 Product perspectiveWG-DPEC-1.0 board acts as data acquisition and signal processing unit to achieve closed loopfunctionality of FOG. This will be used for rotation rate computation using FOG as a sensor.FOG works on the principle of Sagnac phase shift. The output of the FOG is characterized by theequation:

Y(t) = 1+ cos (R(t) + B(t))Where Y(t) is output in terms of Sagnac phase shift in radians,

R(t) is rate of rotation in rad/secB(t) is biasing signal

CLFOG is biased with square wave signal of period equal to transit time of the fiber-coil.The PINFET converts optical power, which is output of FOG to electrical signal. This output is squarewave modulated co-sinusoidal signal.The modulated Sagnac Phase shift data is received through PINFET output of CLFOG.

On-board 16-bit ADC will receive the data from PINFET and will be processed to generate the feedbacksignal for the phase modulator is given through 16-bit DAC. This feed back signal represents phase-error-compensation signal to achieve closed loop functionality of the system.FPGA is used in interfacing with various components, performing digital signal processing functions andcommunicating with user interface.

The FPGA firmware mainly consists of following three sections:1) Control and clock signal generation2) Algorithm implementation3) Communication with external world using UART protocol

Figure 1: Block diagram of DPEC system

WG-DPEC-1.0

Fiber

OpticGyroscope

HOST



2.2 End users perspective

WG-DPEC-1.0 board acts as data acquisition and signal processing unit to achieve closed loopfunctionality of FOG. It provides feed back phase nullifying signal and bias to the modulator (IOC) of the

FOG. It accepts modulated Sagnac phase error signal from the photo detector of gyro and performssynchronous demodulation to extract the Sagnac phase error. It integrates (in phase integrator) thedemodulated Sagnac phase error to generate stair case feed back phase nullifying signal again. It formsclosed loop functionality with an integral controller. The WG-DPEC-1.0 board transfers the phaseintegrator output to the host by compensating the temperature induced bias errors, upon the request ofsynchronization pulses.

Figure 2 : End users perspective

2.3 Assumptions and dependencies

• The bias frequency generated by this unit depends on the multiplier and divider constantsacceptable by the DCM of the FPGA used.

• Look up table based compensation algorithm used for bias compensation

• The system clock should have minimum jitter for proper operation of DCM.

• UART baud rate accuracy depends on the accuracy of the 1.8432 MHz crystal used and the DCM

WG-DPEC-1.0 system functionality• Synchronous demodulation of gyro output.• Integration of phase error• Feed back phase nullifying ramp signal generation• Bias signal generation

• Bias compensation against temperature• Scale factor normalization

Photo detector output

Synchronization pulse

Ramp signal to IOC

Bias signal to IOC

Serial data to host



3. Design constraints

3.1 Software constraints

• The pin assignment should be according to the schematic and proper IO standard should be set.

• Wherever possible the logic will make use of in built features of FPGA such as block RAM, DCM,multiplier macros constructed with FPGA primitives etc.

3.2 Hardware constraints

• Clock should not contain glitches.

• Voltage levels at I/O should match with the interface.

• Power supply should be ripple free.

4. Risk and Issues

Nil

The intended firmware is to measure the angular rotation rate using closed loop algorithm.In this, modulated phase error data coming from gyro optical module (via ADC) is synchronouslydemodulated and passed through a moving average filter. The result is integrated with the transit timereference to get final step size, which will be further used for generation of staircase ramp. This staircaseramp signal is used as a feedback signal to nullify the rotation rate induced Sagnac phase shift of gyroand it is applied to IOC. The peak to peak output voltage of staircase ramp is equal to V2π voltage of IOCused for phase modulation of gyro. A square wave biasing signal is also applied to IOC for intensitymodulation. The peak to peak amplitude of square wave is π /2 volts of IOC.

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