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Section I. Implementing Custom Memory Interface PHY

External Memory Interface Handbook Volume 5

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External Memory Interface Handbook Volume 5 Section I.Implementing Custom Memory Interface PHY
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External Memory Interface Handbook Volume 5 December 2010 Altera Corporation


2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.& Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respectiveholders as described at www.altera.com/common/legal.html.Altera warrants performance of its semiconductor products to current specifications in accordancewith Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility orliability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Alteracustomers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products orservices.
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December 2010 Altera Corporation External Memory Interface Handbook Volume 5


Contents

Chapter 1. Creating a Custom PHY

Instantiate the ALTPLL Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Clocking Scheme Requirement for Full-Rate Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DLL Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Resynchronize Postamble Clock (resync_postamble_clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Write Clock (write_clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Memory Clock (mem_clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Address/Command Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Clocking Scheme Requirement for Half-Rate Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15DLL Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Resynchronize Postamble Clock (resync_postamble_clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Write Clock (write_clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Memory Clock (mem_clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PHY Clock (PHY_clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Address and Command Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Instantiate ALTDLL Megafunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Instantiate ALTDQ_DQS Megafunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MegaWizard Plug-In Manager Options for ALTDQ_DQS Megafunction for Full-Rate and Half-RateSettings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Instaniate the ALTOCT Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118Create Controller Logic for the Read and Write Datapaths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Create Controller Logic for Address and Command Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Create Controller Logic for the OCT Calibration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Instantiate ALTIOBUF Megafunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Connect all Instances Used in Custom External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Add Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Pin Locations, DQ Group Assignments, and I/O Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Pin Loading, Termination, and Drive Strength Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Plan Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Advanced IO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Perform RTL or Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Compile Design and Verify Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Adjust Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Chapter 2. Implementing a CustomDDR2 SDRAM Interface

Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Create a Quartus II Project and Specify a Target Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Instantiate the PHY and Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Instantiate ALTPLL Megafunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Instantiate the ALTDLL Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Instantiate ALTDQ_DQS Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Specify altdq_dqs_1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Design Customized Memory Controller Datapath Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Multiplxer Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

cmd_addr_mux_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28dqs_dqsn_dq_dmr_mux_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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iv Contents



Design Customized Memory Controller Control Path Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Instantiate ALTIOBUF Megafunctions for Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Connect All the Instances That are Used in the Custom External Memory Interface . . . . . . . . . . . 210

Add Constraints to Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210Add Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210Set Top-Level Entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Set Optimization Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211Set Fitter Effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211Enter Pin Location Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211Board Trace Delay Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Perform RTL or Functional Simulation (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Compile Design and Verify Timing for Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Adjust Constraints for this Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Verifying Design on a Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Additional InformationDocument Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1
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1. Creating a Custom PHY

This chapter describes the FPGA design flow to implement a memory interface

datapath (PHY) using Stratix III and Stratix IV devices and the ALTDLL andALTDQ_DQS megafunctions. You can use this method as an alternative to using theavailable external memory interface IP. You can then connect this PHY with a custommemory controller to interface with other memory components.

1 Altera recommends using the available external memory IPs instead of using theALTDLL and ALTDQ_DQS megafunctions whenever possible.

f The ALTDLL megafunction implements the dedicated DQS circuitry, while theALTDQ_DQS megafunction implements the read and write PHY required for theinterface. For more information about these megafunctions, refer to theALTDLL andALTDQ_DQS Megafunctions User Guide.

You must constrain the timing of the PHY when using ALTDLL and ALTDQ_DQSmegafunctions. This chapter does not cover details of the timing constraints; however,it includes information about timing analysis and board-level constraints thatdemonstrate and validate the interface.

The design flow steps in this chapter focus on the "Instantiate PHY and Controller"step of the Recommended Design Flowchapter of the External Memory Handbook. You canadapt the steps for a DDR2 SDRAM interface to create other types of memoryinterfaces.

After selecting the appropriate device and memory type, create a project in theQuartus II software that targets the device and memory type. When instantiating the

datapath for DDR and DDR2 SDRAM interfaces in Stratix III and Stratix IV devices,Altera recommends using the ALTDLL and ALTDQ_DQS megafunctions for thedatapath of custom external memory interfaces that are not supported by theALTMEMPHY or UniPHY IP.

You use the following megafunctions to create a complete memory interface PHY:

ALTDLL megafunction

ALTDQ_DQS megafunction

ALTPLL megafunction

ALTIOBUF megafunction

ALTOCT megafunction

The following sections describe the work flow when you instantiate PHY via ALTDLLand ALTDQ_DQS megafunctions and your custom-designed controller in aQuartus II project:
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12 Chapter 1: Creating a Custom PHY

Instantiate the ALTPLL Megafunction



Instantiate the ALTPLL MegafunctionThe ALTPLL instance provides the necessary clocking scheme for the custom PHY.Clocking schemes for the custom external memory interface are important. You mustunderstand what clocks are required for a full-rate or half-rate interface. Bothinterfaces require different clocking schemes.

Clocking Scheme Requirement for Full-Rate Interface

Figure 11 on page 12shows ta sample full-rate interface.

Figure 11. Example Full-Rate Interface

D5OCT

D6OCT

D5

D6

D1

D6 D5

DDIO_IN

DQ

DDIO_OE(extended_rtena) rtena

DQ OE

WriteData

ReadData

FF(oe)

DDIO_OUT

INPUT_PHASE_ALIGN

INPUT_PHASE_ALIGN

D5OCT

D5

D6D6

OCT

D6 D5

Da

Db

DQS DelayChain

DQS

DDIO_OE(extended_rtena) rtena

DQ OE

DQSEnable

DQSOutput

DDIO_OE

DDIO_OUT

DQSENABLE

DQSEnableControl

DLL OffsetControl

DLL

PLL mem_clk

write_clk

resync_postamble_clk

6 6
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Chapter 1: Creating a Custom PHY 13




The PLL instance should generate the following five clock outputs for the full-rateinterface (refer to Figure 11):

DLL Input clock

Resynchronize postamble clock (resync_postamble_clk)

Write Clock (write_clk) Memory clock (mem_clk)

Address/command clock

The following sections descibe each of the five clock outputs for the full-rate interface.

DLL Input Clock

This clock toggles the DLL block. The DLL clock is equivalent to the full rate of theinterface and has a 0 phase shift. You must connect the DLL block directly to a singlededicated PLL clock output.

Resynchronize Postamble Clock (resync_postamble_clk)The resync_postamble_clkclock is an optional clock.

You can use this clock for two purposes:

Clock the DQS enable control block. This block is used to disable the DQS inputstrobe when the strobe goes to Hi-Z (after a DDR read postamble). This is part ofthe DQS input path.

Clock the INPUT_PHASE_ALIGN block. This block phase shifts the input signaland is primarily used to match the arrival delay of the DQS to the latest arrivaldelay of a DQS from the DDR or DDR2 DIMM. It is also used to resynchronize thedata read from the DDIO_IN block. This is part of the DQ input path.

The resync_postamble_clkclock should be the full rate of the interface and havedynamic phase. You can set the dynamic phase capability for the PLL clock outputswith the ALTPLL megafunction. The correct resync_postamble_clkclock phase iscrucial to correct data transfer. The ALTDQ_DQS megafunction cannot determine thephase that the resync_postamble_clkclock should have. Therefore, you must solvethis with round-trip delay analysis or creating a custom data training circuitry towrite and read back a training pattern to and from the memory device, and thendynamically adjust the resynchronization clock phase of the PLLs to find a goodworking phase.

Write Clock (write_clk)

The write_clkclock clocks the DDIO_OUT block that is part of the DQ output path.The clock is used for writing data to the DQ pins and also to clock the FF (oe) block(refer to Figure 11 on page 12), which is part of the DQ OE path. The FF (oe) blockacts as the output enable for the DQ output path.

The write_clkclock should be the full rate of the interface and have a 90 phaseshift. This ensures the write DQ data is center-aligned with respect to the DQS writestrobe.
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Memory Clock (mem_clk)

The mem_clkclocks the following blocks:

DDIO_OUT block that is part of the DQS output path and

DDIO_OUT blocks that generate the CKand CK#signals.

DDIO_OE block that is part of the DQS OE path

DDIO_OE (extended_rtena) block that is part of the dynamic termination for theDQS pin

DDIO_OE (extended_rtena) block that is part of the dynamic termination for theDQ pin

The mem_clkshould be the full rate of the interface and typically have 0 phase shift.

Address/Command Clock

The address/command clock is used to clock the DDIO_OUT blocks that are used forthe address and command pins. Although not shown in Figure 11 on page 12, it is

discussed further in Create Controller Logic for Address and Command Pins onpage 121.

The address/command clock should be the full rate of the interface and have a 180phase shift. The 180 value is dependent on the address/command/control signalsbeing perfectly matched to the clock signals in time delay on the PCB. Typically, this isnot the case, but it is ideal.


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Clocking Scheme Requirement for Half-Rate Interface

Figure 12shows a sample half-rate interface.

The PLL instance for a half-rate interface generates the following six clock outputs(refer to Figure 12):

DLL input clock

Figure 12. Example Half-Rate Interface

D5

OCT

D6

OCT

D5

D6

D1

D6 D5

DDIO_IN

DQ

DDIO_OE

(extended_rtena)

DDIO_OUT(half_rate_mode=true) rtena

FF(oe)

DDIO_OUT

INPUT_

PHASE_ALIGN

INPUT_

PHASE_ALIGN

D5

OCT D5

D6D6

OCT

D6 D5

Da

Db

DQS Delay

Chain

DQS

DDIO_OE

(extended_rtena)

DDIO_OE

DDIO_OUT

DQS

ENABLE

DQS

Enable

Control

I/O Clock

Divider

DLL Offset

Control

DLL

PLL mem_clk

write_clk

resync_postamble_clk

PHY_clk (half-rate)

6 6

2

DDIO_OUT

(half_rate_mode=true)

DQ OE

2

DDIO_OUT


Write

Data

Read

Data

2

DDIO_OUT


Half-Rate Input

2

DDIO_OUT

(half_rate_mode=true) 2

DDIO_OUT


DDIO_OUT


DDIO_OUT


DDIO_OUT


4

rtena

DQS OE

DQS

Output

DQS

Enable

half-rate resync_clk


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Resynchronize postamble clock (resync_postamble_clk)

Write clock (write_clk)

Memory clock (mem_clk)

PHY Clock (PHY_clk)

Address/command clock

The following sections describe the details of the six clock outputs for the half-rateinterface.

DLL Input Clock

The DLL clock is used to toggle the DLL block. The DLL clock should be equivalent tothe full rate of the interface and have a 0 phase shift. You must connect the DLL blockdirectly to a single dedicated PLL clock output.

Resynchronize Postamble Clock (resync_postamble_clk)

The resync_postamble_clkclock is an optional clock. You can use this clock for threepurposes:

Clock the DQS enable control block. The DQS enable control block is used todisable the DQS input strobe after the strobe goes to Z (after a DDR readpostamble). This is part of the DQS input path.

Clock the INPUT_PHASE_ALIGN block. This block phase shifts the input signaland is primarily used to match the arrival delay of the DQS to the latest arrivaldelay of a DQS from the DDR or DDR2 DIMM. It is also used to resynchronize thedata read from the DDIO_IN block.

Feed the I/O clock divider block that is a part of the DQS input path. The I/Oclock divider divides the clock by two (half-rate resync_clk) and uses it to clockthe DDIO_OUT (half_rate_mode=TRUE) block that is part of the DQS input path.The DQS input path controls the DQS enable signal and also clocks the half-rateinput block that is part of the DQ input path.

The resync_postamble_clkclock should be the full rate of the interface and havedynamic phase. You can set the dynamic phase capability for the PLL clock outputswith the ALTPLL megafunction. The correct resync_postamble_clkclock phase iscrucial to correct data transfer. The ALTDQ_DQS megafunction cannot determine thephase that the resync_postamble_clkshould have. Therefore, you must solve thiswith RTD analysis or creating a custom data training circuitry to write and read back atraining pattern to and from the memory device and then dynamically adjust theresynchronization clock phase of the PLLs to find a good working phase.

Write Clock (write_clk)

The write_clkclocks the DDIO_OUT block that is a part of the DQ output path. TheDDIO_OUT block is used for writing data to the DQ pins and to clock the FF (oe)block that is a part of the DQ OE path. The FF (oe) block (refer to Figure 12) acts asthe output enable for the DQ output path.

The write_clkshould be the full rate of the interface and have about a 90 phaseshift. This requirement ensures the write DQ data is center-aligned with respect to theDQS write strobe.


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Memory Clock (mem_clk)

The mem_clkclocks the following blocks:

DDIO_OUT block that is part of the DQS output path

The memory clock is also used to clock the DDIO_OUT blocks that generate the CK

and CK#signals. DDIO_OE block that is part of the DQS OE path

DDIO_OE (extended_rtena) block that is part of the dynamic termination for theDQS pin

DDIO_OE (extended_rtena) block that is part of the dynamic termination for theDQ pin

The memory clock should be the full rate of the interface and have about a 0 phaseshift.

PHY Clock (PHY_clk)

The PHY_clkclocks the following blocks:

Two DDIO_OUT (half_rate_mode=TRUE) blocks that are part of the DQS outputpath

DDIO_OUT (half_rate_mode=TRUE) block that is part of the DQS OE path

DDIO_OUT (half_rate_mode=TRUE) block that is part of the dynamic terminationfor the DQS pin

Two DDIO_OUT (half_rate_mode=TRUE) blocks that are part of the DQ outputpath

DDIO_OUT (half_rate_mode=TRUE) block that is part of the DQ OE path

DDIO_OUT (half_rate_mode=TRUE) block that is part of the dynamic terminationfor the DQ pin

The PHY_CLKshould be the half rate of the interface and have a 0 phase shift.

Address and Command Clock

The address and command clock clocks the DDIO_OUT blocks that are used for theaddress and commend pins. Although not shown in Figure 12 on page 15, it isdiscussed further in Create Controller Logic for Address and Command Pins onpage 121.

The address and command clock should be the full rate of the interface and have a

phase shift between 180 and 359. The value is dependent on theaddress/command/control signals being perfectly matched to the clock signals intime delay on the PCB. Typically, this is not the case, but it is ideal.

f For more information about using PLLs or other blocks, refer to theALTPLLMegafunction User Guide.

After you decide on your clocking scheme as discussed in this section, you canproceed to the next step.
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Instantiate ALTDLL Megafunctions



Instantiate ALTDLL MegafunctionsUsing the MegaWizard Plus-In Manager, instatiate an ALTDLL megafunction thatcorresponds with the memory interface frequency. You must set the input frequency,delay chain length, and delay buffer mode for the DLL in the MegaWizard interface.Specify a DLL frequency mode that corresponds with the middle frequency range of

the DLL frequency mode. This DLL frequency mode determines the delay buffermode and delay chain length of interface. You can also specify a jitter reduction for theDLL offset control blocks.

f Refer to the "DLL and DQS Logic Block Specifications" section of the the Stratix IIIDevice Datasheet or theStratix IV Device Datasheet.

f For more information about the settings in this section, refer to the MegaWizardPlug-In Manager Page Descriptions for the ALTDLL Megafunction section of theALTDLL and ALTDQ_DQS Megafunctions User Guide.

Instantiate ALTDQ_DQS MegafunctionsAfter configuring the DLL settings, you must set the dedicated circuitry settings forexternal memory interfaces with the ALTDQ_DQS megafunction.

A typical custom external memory interface consists of the following:

Zero or one DQS I/O pin (read or write strobe/clock) with an optional DQSn I/Opin (differential strobe/clock), or a CQ and CQn I/O pair (complementary clock)

One or more DQ I/O pins (read or write data)

One DM/D pin (output-only data mask, write data, or both)

The ALTDQ_DQS megafunction allows you to instantiate a group of DQ pins

(ranging from 4 to 36) along with their corresponding DQS block, or DQSn I/O(optional) block, or both (optional). The ALTDQ_DQS megafunction enables you togenerate the necessary DQ/DQS circuitry to use with external memory interfaces.You can configure the DQS and DQSn I/O as input-only, output-only, or bidirectionalpins. All bidir_dqI/O pins are identically configured. Similarly, all output_dq(output-only DQ/DM I/O pins) and input_dqI/O pins (input-only DQ pins) areidentically configured. Hence, if delay chains or half-data rate blocks are used in apath, the configuration applies to all paths of the same type. The paths can be all-input paths, all-output paths, or bidirectional paths in the ALTDQ_DQS variation.The ALTDQ_DQS megafunction generates only one DQS I/O pin per instantiation. Ifyou need a 72-bit data interface composed of 9 data groups, you must generate a 9data group with the megafunction and then instantiate it eight times.

The following steps describe the general flow when using the ALTDQ_DQSmegafunction:

1. Configure the general settings for the ALTDQ_DQS instances, which includes thenumber of input, output, and bidirectional DQ, DQS delay chain stages, DQSinput frequency, use half-rate components, and use dynamic OCT path.

2. Configure the DQS input path, which includes using input delay chain (D1), usingDQS delay chain, enabling DQS busout delay chain, enabling DQS enable block,enabling DQS enable control block, and enabling DQS enable block delay chain.
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Instantiate ALTDQ_DQS Megafunctions



3. If you enable the DQS delay chain block to true, the DQS Delay Chain Settingsdialog box appears. You must configure the DQS delay chain settings.

4. If you enable the DQS enable control to true, the DQS Enable Control Settingsdialog box appears. You must configure the DQS enable control settings.

5. Configure the DQS output/OE path, which includes enabling DQS output delay

chain 1 (D5), enabling DQS output delay chain 2 (D6), configuring DQS outputregisters, enabling DQS OE delay chain 1 (D5), enabling DQS OE delay chain 2(D6), and configuring the DQS OE registers.

6. Configure the DQ input path, which includes configuring the DQ input registers,selecting the clock source for the DQ input register, enabling the DQ input phasealignment block, use the DQ half-rate dataoutbypassport, and enabling the DQinput delay chain (D1).

7. If you enable the DQ input phase alignment block to true, the DQ Input PhaseAlignment Block Settingsdialog box appears. You must configure the DQ inputphase alignment block settings.

8. Configure the DQ output/OE path, which includes enabling DQ output delaychain 1 (D5), enabling DQ output delay chain 2 (D6), configuring the DQ outputregisters, enabling DQ OE delay chain 1 (D5), enabling DQ OE delay chain 2 (D6),and configuring the DQ OE registers.

9. Configure the half-rate components, which includes configuring the IO clockdivider block, source clock, creating the io_clock_divider_masterininput portfor chaining multiple IO_CLOCK_DIVIDER blocks, enabling theio_clock_divider_clkoutoutput port for clocking core registers, enabling theio_clock_divider_slaveoutoutput port for chaining multipleIO_CLOCK_DIVIDER blocks, and inverting the phase through this block.

10. Configure the Dynamic OCT components, which includes enabling OCT delay

chain 1(D5 OCT), enabling OCT delay chain 2(D6 OCT), and configuring OCTregister mode.

11. Configure the DQS/DQSn IO,which includes configuring the DQS/DQSn pair asa differential pair or complementary pair.

12. Configure the reset ports for the ALTDQ_DQS instance. The configuration enablesthe asynchronous and synchronous reset ports to all the registers in the DQS andDQ datapath.

Table 11shows two examples of the ALTDQ_DQS settings.

Table 11. ALTDQ_DQS Interface Example Settings (Part 1 of 2)

Settings Full-Rate Interface Half-Rate InterfaceDevice Stratix III, speed grade C3 Stratix III, speed grade C3

DQS/DQSn 1 bidirectional differential DQS/DQS 1 bidirectional differential DQS/DQS

DQ Pins 8 bidirectional DQ pins 8 bidirectional DQ pins

DM Pins 1 output DM pin 1 output DM pin

DQS Frequency 155 MHz 450 MHz

Using dynamictermination path

Yes Yes

Using half-rate blocks No Yes
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MegaWizard Plug-In Manager Options for ALTDQ_DQS Megafunction forFull-Rate and Half-Rate Settings

This section provides descriptions of the options available on the individual pages ofthe ALTDQ_DQS MegaWizardPlug-In Manager for both full-rate and half-rateinterfaces, as shown in Figure 11 on page 12and Figure 12 on page 15.

On page 3 of the ALTDQ_DQS MegaWizard Plug-In Manager, you can select optionson the Parameter Settingspage as shown in Table 12.

DQS delay chain phaseshift

90 90

delay_chain_length for

DLL 12 8

DLL has offset controlblocks enabled

Yes Yes

Data rate of interface 310 Mbps 900 Mbps

Table 11. ALTDQ_DQS Interface Example Settings (Part 2 of 2)

Settings Full-Rate Interface Half-Rate Interface

Table 12. Parameter Settings (Part 1 of 2) (Note 1)

Option (2) Full-Rate Interface Half-Rate Interface

Number of bidirectionalDQ

8. There are 8 DQ pins for the interface. 8. There are 8 DQ pins for the interface.

Number of input DQ 0. This option is not used for the interface. 0. This option is not used for the interface.

Number of output DQ 1. This is used for the 1 DM output pin. 1. This is used for the 1 DM output pin.

Number of stages indqs_delay_chain

3. Center the DQS strobe signal with the DQdata (DQS signal must be 90 phaseshifted). This setting depends on theintended phase shifted (90) and the DLLdelay chain length (12).

2. Center the DQS strobe signal with the DQ data(DQS signal must be 90 phase shifted). Thissetting depends on the intended phase shifted(90) and the DLL delay chain length (8).

DQS Input FrequencyEnter 155 MHz. This value must match theinput frequency for the DLL instance (viaALTDLL).

Enter 450 MHz. This value must match the inputfrequency for the DLL instance (via ALTDLL).

Use half rate componentsTurn off this option. This option is notapplicable for the full-rate interface.

Turn on this option.

Turning on this option enables the following 11half-rate components.
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Table 13shows the settings needed to achieve particular phase shifts for the DQSdelay chain block mentioned in Table 12:

Setting the DQS delay chain phase is one of the most important parts of theALTDQ_DQS megafunction. It determines the necessary phase shift in the DQS delaychain that clocks the DDIO_IN block in the DQ input path. This requires a phase shift

of 90 to center align the DQS strobe with the DQ data. Consider the followingscenarios:

Scenario One

If you are using a Stratix III device with C3 speed grade, refer to theStratix III Device Handbookfor the appropriate settings.

Because the DQS input frequency for the first scenario is 155 MHz, the devicespeed grade is C3, the DLL delay chain length is 12, delay buffer mode is low, andthe intended phase shift is 90. For these parameters, set the Stages of the DQSDelay Chainoption to 3.

Scenario Two

For a particular DLL delay chain length, you might not get your intended phasesetting.

For example, set the DLL delay chain length to 10 and the DQS input frequency to190 MHz. Your intended phase setting is 90, but the closest available is a 72phase shift, which is DQS delay stages setting of 2. Instantiate the DLL offsetcontrol blocks (ALTDLL) to introduce the necessary offset to the DQS delay chainto achieve the intended 90 phase shift.

Page 4 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQS INAdvancedOptionspage. Table 13shows how to configure the DQS input path of theALTDQ_DQS instance.

Use dynamic OCT path (3)Turn on this option. Turning on this optionenables the following two dynamic OCTcomponents.

Turn on this option. Turning on this optionenables the following four dynamic OCTcomponents.

Notes to Table 12:

(1) For more information about these options, refer to the ALTDQ_DQS High-Level Configuration Settings and MegaWizard Plug-In ManagerPage Descriptions for the ALTDQ_DQS Megafunction sections in the ALTDLL and ALTDQ_DQS Megafunctions User Guide.

(2) You can use differential or complementary mode instead of single-ended mode for the DQS IO.

(3) With dynamic OCT, you can enable the parallel termination (Rt) during reads from the DDR and DDR2 external memory, and disable the Rtduring writes from the DDR and DDR2 external memory. This significantly reduces power consumption for external memory interfaces.

Table 12. Parameter Settings (Part 2 of 2) (Note 1)


Table 13. DQS IN Advanced Options Page (Part 1 of 3)


Enable DQS Input Path(2)

Turn on this option. Turning on this optiongives you the access to the five blocks in theDQS input path as shown in Figure 11 onpage 12

Turn on this option. Turning on this optiongives you the access to the six blocks in theDQS input path as shown in Figure 12 onpage 15.

Delay chain usage:(Enable dynamic delaychain)

Turn off this option. This option is notapplicable for this interface.

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Delay chain usage:(Enabledqs_delay_chain)

Turn on this option. Turning on this optionenables the DQS delay chain block.

Turn off this option. Turning off this optionenables the DQS delay chain block.

Advanced Delay ChainOptions(DQS Delay Chain PhaseSetting Options)

Turn off the Set dynamically usingconfiguration registersoption.

Turn off the Set dynamically usingconfiguration registersoption.

Advanced Delay ChainOptions(DQS Delay Chain PhaseSetting Options)

Select the DLLoption. This allows DLL tocontrol the delay in the DQS delay chain block.

Select the DLLoption. This allows DLL tocontrol the delay in the DQS delay chain block.

Advanced Delay ChainOptions(DQS Delay BufferMode)

Select the Lowoption. This must be set to lowbecause this must match the delay buffermode of the DLL which is used for full-rateinterface.

Select the Highoption. This must be set tohigh because this must match the delay buffermode of the DLL which is used for half rateinterface.

Advanced Delay ChainOptions(DQS Phase Shift) (3)

Enter 9,000for 90. The phase shift for theinterface.

Enter 9,000for 90. The phase shift for theinterface.

Advanced Delay ChainOptions(Enable DQS offsetcontrol)

Turn on this option. This allows the offsetsettings (6-bit output) from the DLL offsetcontrol block to control the DQS delay chainblock in.

Turn on this option. This allows the offsetsettings (6- bit output) from the DLL offsetcontrol block to control the DQS delay chainblock.

Advanced Delay ChainOptions:(Enable DQS delay chainlatches)



Enable DQS busout

delay chain (2)

Turn on this option. Turning on this option

enables the Da block.

Turn on this option. Turning on this option

enables the Da block.

Enable DQS enable block(4)

Turn on this option. This is used to enable ordisable the DQS signal.

Turn on this option. This is used to enable ordisable the DQS signal.

Enable DQS enablecontrol block

Turn on this option. This is used to control theDQS enable block.

Turn on this option. This is to control the DQSenable block.

Advanced EnableControl Options(DQS Enable ControlPhase Setting)

Select the Set statically to 0option. Thedelay here is set to the static value of zero.

Select the Set statically to 0option. Thedelay here is set to the static value of zero.

Advanced EnableControl Options

(DQS Enable ControlInvert Phase)

Select the Never option. Select the Never option.


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Page 5 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQS OUT/OEAdvanced Optionspage. Table 14shows how to configure the DQS OUTPUT andDQS OE path of the ALTDQ_DQS instance.

Enable DQS enable blockdelay chain (2)

Turn on this option. Turn on this option.

Notes to Table 13:

(1) For more information about these options, refer to the Configuring the DQS Input Path and MegaWizard Plug-In Manager Page Descriptionsfor the ALTDQ_DQS Megafunction sections in the ALTDLL and ALTDQ_DQS Megafunctions User Guide.

(2) Da represents the DQSBUSOUT_DELAY_CHAIN block and Db represents the DQSENABLE_DELAY_CHAIN block.

(3) This setting is meant for timing analysis. This informs the TimeQuest timing analyzer to analyze the delay through the DQS delay chain blockas the corresponding phase shift.

(4) The DQS enable represents the AND-gate control on the DQS input used to enable the DQS input strobe after the strobe goes to Z (after a DDRread postamble).



Table 14. DQS OUT/OE Advanced Options Page


Enable DQS output path (2)Turn on this option. Turning on this optiongives you the access to the three blocks inthe DQS output path.

Turn on this option. Turning on this optiongives you the access to the three blocks in theDQS output path.

DQS Output Path Options(Enable DQS output delaychain1) (2)

Turn on this option. Turning on this optionenables the D5 block.


DQS Output Path Options:(Enable DQS output delaychain2) (2)



DQS Output Path Options:(DQS output register mode)

Select the DDIOoption. This sets the

DDIO_OUT block that is part of the DQSoutput path in to a DDIO_OUT.

Select the DDIOoption. This sets the

DDIO_OUT block that is part of the DQSoutput path in to a DDIO_OUT.

DQS Output Enable Options(Enable DQS output enable)(2)

Turn on this option. Turning on this optiongives you the access to the three blocks inthe DQS OE path.

Turn on this option. Turning on this optiongives you the access to the three blocks in theDQS OE path.

DQS Output Enable Options(Enable DQS output enabledelay chain1) (2)

Turn on this option. Turning on this optionenables the D5 block. This is part of the DQSOE path.

Turn on this option. Turning on this optionenables the D5 block. This is part of the DQSOE Path.

DQS Output Enable Options(Enable DQS output enabledelay chain2) (2)



DQS Output Enable Options(DQS output enable registermode)

Select the DDIOoption. This sets theDDIO_OUT block this is part of the DQS OEpath to a DDIO_OUT.

Select the DDIOoption. This sets theDDIO_OUT block that is part of the DQS OEpath to a DDIO_OUT.

Notes to Table 14:

(1) For more information about these options, refer to the Configuration the DQS Output Path, Configuration the DQS OE Path and MegaWizardPlug-In Manager Page Description for the ALTDQ_DQS Megafunction sections in the ALTDLL and ALTDQ_DQS Megafunction User Guide.

(2) D5 block is dynamic output delay chain1 and D6 block is dynamic output delay chain 2. These delay chains are configured dynamically duringFPGA run-time to deskew the DQS pins, providing improved timing margins. For more information about delay chains, refer to the Delay ChainsFor External Memory Interfaces section in the ALTDLL and ALTDQ_DQS Megafunctions User Guide.
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Page 6 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQ IN AdvancedOptionspage. You can select options based on Table 15. This page configures the DQinput path of the ALTDQ_DQS instance.

Table 15. DQ IN Advanced Options Page (Part 1 of 2)


Enable DQS InputPath (2), (4), (5)

Turn on this option. Turning on this option givesyou the access to the four blocks in the DQ inputpath.

Turn on this option. Turning on this option givesyou the access to the five blocks in the DQ inputpath .

DQ Input RegisterOptions(DQ input registermode)

Select the DDIOoption. This sets the DDIO_INblock that is part of the DQ input path.

Select the DDIOoption. This sets DDIO_IN blockthat is part of the DQ input path.

DQ Input RegisterOptions(DQ input registerclock source) (3)

Select the dqs_bus_out portoption and turn offthe Connect DDIO clkn to DQS_BUS fromcomplementary DQSn option. This is used forthe DDIO_IN block.

Select the dqs_bus_out portoption and turn offthe Connect DDIO clkn to DQS_BUS fromcomplementary DQSnoption. This is used for theDDIO_IN.

DQ Input RegisterOptionsUse DQ inputphase alignment(4)

Turn on this option. Turning on this optionenables two INPUT_PHASE_ALIGN blocks thatare part of the DQ input path. This is part of theDQ input path.

Turn on this option. Turning on this optionenables two INPUT_PHASE_ALIGN blocks thatare part of the DQ input path. This is part of theDQ Input Path.

Advanced DQ IPAoptions(DQ Input PhaseAlignment PhaseSetting)

Select the Set statically to 0option. The delay isset to the static value of zero. This is used for thetwo INPUT_PHASE_ALIGN blocks that are part ofthe DQ input path.

Select the Set statically to 0option. The delay isset to the static value of zero. This is meant for thetwo INPUT_PHASE_ALIGN blocks that are part ofthe DQ input path.

Advanced DQ IPAoptions

(Add DQ InputPhase AlignmentInput Cycle Delay)

Select the Never option. This option is only used

for the two INPUT_PHASE_ALIGN blocks that arepart of the DQ input path.

Select the Never option. This option is only used

for the two INPUT_PHASE_ALIGN blocks that arepart of the DQ input path.

Advanced DQ IPAoptions(Invert DQ InputPhase AlignmentPhase)

Select the Neveroption. This option is only usedfor the two INPUT_PHASE_ALIGN blocks that arepart of the DQ input path.

Select the Neveroption. This option is only usedfor the two INPUT_PHASE_ALIGN blocks that arepart of the DQ input path.

Advanced DQ IPAoptions(Register DQ inputphase alignment

bypass output)

Turn off this option. This option is only used fortwo INPUT_PHASE_ALIGN blocks that are part ofthe DQ input path.

Turn off this option. This option is only used fortwo INPUT_PHASE_ALIGN blocks that are part ofthe DQ input path.

Advanced DQ IPAoptions(Register DQ inputphase alignmentadd phase transfer)

Turn off this option. This option is only used forthe two INPUT_PHASE_ALIGN blocks that arepart of the DQ input path.

Turn off this option. This option is only used forthe two INPUT_PHASE_ALIGN blocks that arepart of the DQ input path.

Use DQ half ratedataoutbypassport (5)

Turn off this option. This option is only used forthe half-rate input block that is part of the DQinput path.

Turn off this option. This option is only used forthe half-rate input block that is part of the DQinput path.
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Page 7 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQ OUT/OEAdvanced Optionspage. You can select options based on Table 16. This configuresthe DQS OUTPUT and DQS OE path of the ALTDQ_DQS instance.

Use DQ input delaychain (2)

Turn on this option. Turning on this optionenables the D1 block. This is part of the DQ inputpath.

Turn on this option. Turning on this optionenables the D1 block. This is part of the DQ inputpath.

Notes to Table 15:

(1) For more information about these options, refer to the Configuring the DQ Input Path and MegaWizard Plug-In Manager Page Descriptionsfor the ALTDQ_DQS Megafunction sections in the ALTDLL and ALTDQ_DQ Megafunctions User Guide.

(2) D1 block is dynamic input delay chain 1.This delay chain can be dynamically configured during FPGA run-time to deskew the DQ pins, henceproviding improved timing margins. For more information about delay chains, refer to Delay Chains For External Memory Interfaces sectionin the ALTDLL and ALTDQ_DQS Megafunctions User Guide.

(3) You have a choice whether to clock the DQ input registers from the DQS input path (via dqs_bus_outport) or from the FPGA core (viadq_input_reg_clk).

(4) The INPUT_PHASE_ALIGN blocks represent the circuitry required to phase shift the input signal. This is primarily used to match the arrivaldelay of the DQS to the latest arrival delay of a DQS from the DIMM. The phase settings for the INPUT_PHASE_ALIGN blocks must match theI/O clock divider block.

(5) The half-rate input block represents the circuitry required to transfer the input signal to a half-rate clock. One of the outputs can also be switchedto a direct input from the input buffer. This block is use only in half-rate interfaces.

Table 15. DQ IN Advanced Options Page (Part 2 of 2)


Table 16. DQ OUT/OE Advanced Option Page


DQ Output Path Options(Enable DQ output delaychain1) (2)

Turn on this option. Turning on this optionenables the D5 block. This is part of the DQoutput path.

Turn on this option. Turning on this optionenables the D5 block. This is part of the DQoutput path.

DQ Output Path Options(Enable DQ output delay

chain2) (2)

Turn on this option. Turning on this optionenables the D6 block. This is part of the DQ

output path.

Turn on this option. Turning on this optionenables the D6 block . This is part of the DQ

output path.

DQ Output Path Options(DQS output register mode).

Select the DDIOoption. This sets theDDIO_OUT block that is part of the DQoutput path.

Select the DDIOoption. This sets DDIO_OUTblock that is part of the DQ output path.

DQ Output Enable Options(Enable DQ output enable)

Turn on this option. Turning on this optiongives you the access to the three blocks inthe DQ OE path.

Turn on this option. Turning on this optiongives you the access to the three blocks inthe DQ OE path.

DQ Output Enable Options(Enable DQS output enabledelay chain1) (2)

Turn on this option. Turning on this optionenables D5 block. This is part of the DQ OEpath.

Turn on this option. Turning on this optionenables D5 block. This is part of the DQ OEpath.

DQ Output Enable Options(Enable DQ output enabledelay chain2) (2)

Turn on this option. Turning on this optionenables the D6 block in. This is part of theDQ OE path.

Turn on this option. Turning on this optionenables the D6 block. This is part of the DQOE path.

DQ Output Enable Options(DQ output enable registermode).

Select the FFoption. This sets the FF (oe)block that is part of the DQ OE path.

Select the FFoption. This sets FF (oe) blockthat is part of the DQ OE path.

Notes to Table 16:

(1) For more information about these options, refer to the Configuring the DQS Output Path, Configuring the DQ OE Path, and MegaWizardPlug-In Manager Page Descriptions for the ALTDQ_DQS Megafunction sections in the ALTDLL and ALTDQ_DQS Megafunctions User Guide.

(2) D5 block is a dynamic output delay chain 1 and D6 block is dynamic output delay chain 2. These delay chains can be dynamically configuredduring FPGA run-time to deskew the DQS pins, hence providing improved timing margins. For more information about delay chains, refer tothe Delay Chains For External Memory Interfaces section in the ALTDLL and ALTDQ_DQS Megafunctions User Guide.
http://../Vol%20Planning/Master%20Files/Sec%20Planning%20Pin/Master%20Files/emi_plan_pin_COVER.pdfhttp://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://../Vol%20Planning/Master%20Files/Sec%20Planning%20Pin/Master%20Files/emi_plan_pin_COVER.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdf


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Page 8 of the ALTDQ_DQS MegaWizard Plug-In Manager is the Half-Rate AdvancedOptionspage. You can select options based on Table 17. This configures the DQinput path of the ALTDQ_DQS instance.

Table 17. Half-Rate Advanced Options Page


IO Clock Divider Source(2), (3)

This option is not applicable forfull-rate interface.

Select the dqs_bus_out portoption. This uses the clocksource from the DQS input path, divides it by half, andthen clocks the half-rate blocks, which are:

DDIO_OUT (half_rate_mode=TRUE) block that is partof the DQS input path, which controls the DQS enablesignal

Half-rate input block that is part of the DQ input path.This is used for the I/O clock divider block.

Createio_clock_divider_masterin

input port (2), (4)

No. Not applicable for full-rateinterface.

Turn off this option. For this half-rate interface, there isonly one ALTDQ_DQS instance. Therefore, I/O clockdivider blocks are automatically chained in the instance

depending on the amount of DQ pins. This is used for theI/O clock divider block .

Createio_clock_divider_clkoutoutput port (2), (5)

Turn on this option. This output should clock the coreregisters that are getting the half-rate DQ data from thehalf-rate registers.

Createio_clock_divider_slaveoutoutput port (2)

Turn off this option. For this half-rate interface, there isonly one ALTDQ_DQS instance. Therefore, I/O clockdivider blocks are automatically chained in the instancedepending on the amount of DQ pins. This is used for theI/O clock divider block.

IO Clock Divider InvertPhase (2)

Select the Neveroption. This is used for theIO_Clock_Divider block.

Notes to Table 17:

(1) For more information about these options, refer to the Configuring the DQS Input Path, I/O Clock Divider Primitive, and MegaWizard Plug-In Manager Page Descriptions for the ALTDQ_DQS Megafunction sections in the ALTDLL and ALTDQ_DQS Megafunctions User Guide.

(2) The I/O_Clock_Divider block represents a div-by-2 clock divider for transferring data to the core at one half the speed of the I/O input and outputclock. Each divider can feed up to six pins (a x4 DQS group) in the device. To feed wider DQS groups, multiple clock dividers must be chainedtogether by feeding the slaveoutoutput of one divider to the masterininput of the neighboring pins' divider. The phase settings for theINPUT_PHASE_ALIGN blocks must match the I/O clock divider block.

(3) This is used to clock the IO_CLOCK_DIVIDER sub-block, which is used during ahalf-rate operation.

(4) If enabled, then the masterininput is used to synchronize this divider with another IO_CLOCK_DIVIDER sub-block. If disabled, then thisdivider operates independently (this mode is meant for the master divider for a group of dividers).

(5) Enables the clock output signal divided by 2. It can be connected to the clock input of a half-rate input block or it can feed the FPGA core.
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Page 9 of the ALTDQ_DQS MegaWizard Plug-In Manager is the OCT AdvancedOptionspage. You can select options based on Table 18. This configures the OCTregisters and delay chain settings of the ALTDQ_DQS instance.

Page 10 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQS/DQSn IOAdvanced Optionspage. You can select options based on Table 19.

Table 18. OCT Advanced Options Page


Dynamic OCT Options(Enable OCT delay chain1)(2)

Turn on this option. Turning on this optionenables two D5 OCT blocks. This is part ofthe DQ and DQS dynamic terminationpath.

Turn on this option. Turning on this optionenables two D5 OCT blocks. This is part of theDQ OE Path. This is part of the DQ and DQSdynamic termination path.

Dynamic OCT Options(Enable OCT delay chain2)(2)

Turn on this option. Turning on this optionenables two D6 OCT blocks. This is part ofthe DQ and DQS dynamic terminationpath.

Turn on this option. Turning on this optionenables two D6 OCT blocks. This is part of theDQ OE Path. This is part of the DQ and DQSdynamic termination path.

DQ Output Path Options(OCT register mode)

Select the DDIOoption. This sets twoblocks:

DDIO_OE (extended_rtena) blockthat is part of the dynamic terminationfor the DQS pin

DDIO_OE (extended_rtena) blockthat is part of the dynamic terminationfor the DQ pin.

Select the DDIOoption. This sets four blocks:

DDIO_OE (extended_rtena) block that ispart of the dynamic termination for the DQS

pin

DDIO_OE (extended_rtena) block that ispart of the dynamic termination for the DQpin

DDIO_OUT (half_rate_mode=TRUE) blockthat is part of the dynamic termination for theDQS pin

DDIO_OUT (half_rate_mode=TRUE) blockthat is part of the dynamic termination for theDQ pin.

Notes to Table 18:

(1) For more information about these options, refer to the Configuring the DQ/DQS OCT Path and MegaWizard Plug-In Manager PageDescriptions for the ALTDQ_DQS Megafunction sections in the ALTDLL and ALTDQ_DQS Megafunctions User Guide.

(2) The D5 OCT block is dynamic output delay chain 1 and the D6 OCT block is dynamic output delay chain 2. These delay chains are used togetherwith the D5 block and D6 block. With Dynamic OCT, you can enable R tduring reads from the DDR and DDR2 external memory and disable Rtduring writes from the DDR and DDR2 external memory. This has a benefit of significantly reducing power consumption for external memoryinterfaces. Hence the necessary usage of the D5 OCT block and D6 OCT block to synchronize during reads and writes from both DQ and DQSpins, and improve overall timing margins. For more information about delay chains, refer to the Delay Chains For External Memory Interfacessection in the ALTDLL and ALTDQ_DQS Megafunctions User Guide.

Table 19. DQS/DQSn IO Advanced Options Page

Options (1) Full-Rate Interface Half-Rate Interface

Use DQSn I/O Turn on this option. Turn on this option.

DQS and DQSn IO Configuration mode(2)

Select Differential Pair. This isrequired for this particular scenario.

Select Differential Pair. This is requiredfor this particular scenario

Notes to Table 19:

(1) For more information about these options, refer to the Configuring the DQSn I/O Pin Path and MegaWizard Plug-In Manager PageDescriptions for the ALTDQ_DQS Megafunction sections in the ALTDLL and ALTDQ_DQS Megafunctions User Guide.

(2) For the "Differential pair" configuration, the DQSn I/O is configured in a differential pair along with the DQS IO. This means that the OE and OCTpaths are configured for the DQSn I/O, whereas the input and output paths are shared with the DQS IO.
http://../Vol%20Planning/Master%20Files/Sec%20Planning%20Pin/Master%20Files/emi_plan_pin_COVER.pdfhttp://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://-/?-http://-/?-http://-/?-http://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://../Vol%20Planning/Master%20Files/Sec%20Planning%20Pin/Master%20Files/emi_plan_pin_COVER.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdfhttp://www.altera.com/literature/ug/ug_altdll_altdq_dqs.pdf


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Instaniate the ALTOCT Megafunction



Page 11 of the ALTDQ_DQS MegaWizard Plug-In Manager is the Reset PortAdvanced Optionspage. You can select options based on Table 110.

This completes the settings for both full-rate and half-rate scenarios for theALTDQ_DQS instance.

Instaniate the ALTOCT MegafunctionUse of the OCT scheme in Stratix III and Stratix IV devices eliminates the need forexternal series or parallel termination resistors and simplifies the design of a PCB.Stratix III and Stratix IV devices support calibrated on-chip series, parallel, and

dynamic termination in all I/O banks for single-ended I/O standards. OCTcalibration allows you to establish an optimal termination value that compensates forimpedance change due to temperature and voltage fluctuation. You can calibrateStratix III and Stratix IV devices with user-controlled signals during device operation,or by default during device configuration. For calibrated termination, use theALTOCT megafunction to utilize the dedicated calibration blocks for terminationavailable in the FPGA together with the dedicated OCT in the I/O buffers with theALTIOBUF megafunction.

For custom external memory interfaces, there are significant advantages to using bothdynamic OCT and calibrated termination:

Table 110. Reset Ports Advanced Options Page

Option Full-Rate Interface Half-Rate Interface

Create 'dqs_areset' input portTurn on this option. Turning on thisoption enables asynchronous reset portfor all registers in the DQS datapath.

Turn on this option. Turning on this optionenables asynchronous reset port for allregisters in the DQS datapath.

Create 'dqs_sreset' input portTurn on this option. Turning on thisoption enables synchronous reset portfor all registers in the DQS datapath.

Turn on this option. Turning on this optionenables synchronous reset port for allregisters in the DQS datapath.

Create 'input_dq_areset' inputport

Turn off this option. This option is notapplicable in this scenario because theDQ datapath is bidirectional.

Turn off this option. This option is notapplicable in this scenario because the DQdatapath is bidirectional.

Create 'input_dq_sreset' inputport

Turn off this option. This option is notapplicable in this scenario because theDQ datapath is bidirectional.

Turn off this option. This option is notapplicable in this scenario because the DQdatapath is bidirectional.

Create 'output_dq_areset' inputport

Turn on this option. Turning on thisoption enables asynchronous reset portfor all registers in the DQ datapath. Thisis meant for the DM pin.

Turn on this option. Turning on this optionenables asynchronous reset port for allregisters in the DQ datapath. This is meant forthe DM pin.

Create 'output_dq_sreset' inputport

Turn on this option. Turning on thisoption enables synchronous reset portfor all registers in the DQ datapath. Thisis meant for the DM pin.

Turn on this option. Turning on this optionenables synchronous reset port for allregisters in the DQ datapath. This is meant forthe DM pin.

Create 'bidir_dq_areset' inputport

Turn on this option. Turning on thisoption enables asynchronous reset portfor all registers in the DQ datapath.

Turn on this option. Turning on this optionenables asynchronous reset port for allregisters in the DQ datapath.

Create 'bidir_dq_sreset' inputport

Turn on this option. Turning on thisoption enables synchronous reset portfor all registers in the DQ datapath.

Turn on this option. Turning on this optionenables synchronous reset port for allregisters in the DQ datapath.


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Create Controller Logic for the Read and Write Datapaths



OCT calibration allows you to establish an optimal termination value thatcompensates for impedance change due to temperature and voltage fluctuation.

Simplifies the design of a PCB.

Significant power consumption reduction for external memory interfaces. Withdynamic OCT you can enable Rtduring reads from the DDR and DDR2 external

memory and disable Rtduring writes from the DDR and DDR2 external memoryand when the interface is idle.

You can use the ALTDLL and ALTDQ_DQS custom external memory interfaces toachieve these advantages.

f For more information about using the dynamic calibration blocks for termination,refer to Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction User Guide.

f For more information about using the dynamic OCT, refer to I/O Buffer (ALTIOBUF)Megafunction User Guide.

f For more information about implementing calibrated dynamic OCT, refer toAN 465:Implementing OCT Calibration in Stratix III Devices.

Create Controller Logic for the Read and Write DatapathsConsider the following details when designing the controller for these signals:
http://../Vol%20Planning/Master%20Files/Sec%20Planning%20Pin/Master%20Files/emi_plan_pin_COVER.pdfhttp://-/?-http://-/?-http://www.altera.com/literature/ug/ug_altoct.pdfhttp://www.altera.com/literature/an/an465.pdfhttp://www.altera.com/literature/an/an465.pdfhttp://-/?-http://-/?-http://../Vol%20Planning/Master%20Files/Sec%20Planning%20Pin/Master%20Files/emi_plan_pin_COVER.pdfhttp://www.altera.com/literature/an/an465.pdfhttp://www.altera.com/literature/an/an465.pdfhttp://www.altera.com/literature/ug/ug_altoct.pdf


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Create Controller Logic for the Read and Write Datapaths



General (applies to both full-rate and half-rate interfaces):

The DQ signals are edge-aligned with the DQS signal during a read from thememory and are center-aligned with the DQS signal during a write to thememory.

The memory controller shifts the DQ signals by 90 during a write operation

to center-align the DQ and DQS signals. Center-align the PLL to the DQS signalwith respect to the DQ signals during writes.

The memory controller delays the DQS signal during a read, to ensure that theDQ and DQS signals are center-align at the capture register. Use dedicatedDQS phase-shift circuitry (ALTDLL and ALTDQ_DQS) to shift the incomingDQS signal during reads.

The DQS signal is generated on the positive edge of the system clock to meetthe tDQSSrequirement. The setup (tDS) and hold times (tDH) of the memorydevice for the write DQ and DM pins are relative to the edges of DQS writesignals and not the CK or CK# clock.

DQ and DM signals use a clock shifted 90 from the system clock to ensurethat the DQS edges are centered on the DQ or DM signals when they arrive atthe DDR2 SDRAM.

DDR2 SDRAM uses the DM pins during a write operation. Driving the DMpins low shows that the write is valid. The memory masks the DQ signals if theDM pins are driven high. The timing requirements of the DM signal at theDDR2 SDRAM input are identical to those for DQ data. The Stratix III DDRregisters, clocked by the 90 shifted clock, create the DM signals. While youcan use any of the I/O pins in the same bank as the associated DQS and DQpins to generate the DM signal, Altera recommends using the spare DQ pin inthe same DQS group as the respective data to minimize skew.

Some DDR2 SDRAM DIMMs support error correction coding (ECC) to detectand automatically correct errors in data transmission. The 72-bitDDR2 SDRAM modules contain eight ECC pins in addition to 64-data pins.Connect the eight DDR2 SDRAM device ECC pins to a single DQS or DQgroup.

The DQS, DQ, and DM board trace lengths must be tightly matched (20 ps).

The DQS is bidirectional. The DQSn pins in DDR2 SDRAM devices areoptional but recommended for DDR2 SDRAM designs operating at more than333 MHz.

The DQ pins are also bidirectional. Regardless of interface width,DDR SDRAM always operates in 8 mode DQS groups. DDR2 SDRAMinterfaces can operate in either 4 or 8 mode DQS groups, which is dependanton your chosen memory device or DIMM, and is also not related to the actualinterface width. The 4 and 8 configurations use one pair of bidirectional datastrobe signals, DQS and DQSn, to capture input data.

Two pairs of data strobes, UDQS and UDQS# (upper byte) and LDQS andLDQS# (lower byte), are required by the 16 configuration devices. A group ofDQ pins must remain associated with its respective DQS and DQSn pins.


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Create Controller Logic for Address and Command Pins



Full-rate interface (refer to Figure 11 on page 12):

DQS, DQSn, DM, and DQ signals from FPGA core must be connected to theALTDQ_DQS instance. The ALTDQ_DQS instance interfaces to the externalmemory (DDR and DDR2) for these pins.

Read data from the DQ input path should go through a dual-clock FIFO to

transfer the data from the INPUT_PHASE_ALIGN blocks(resync_postamble_clkclock domain) to the FPGA core clock domain.

Controller has to ensure that the write data from core and DQS output pathstrobe are aligned to ensure that when writing data to external memory, theDQS strobe is center-aligned with the output DQ data to the external memory.

Half-rate interface (refer to Figure 12 on page 15):

DQS, DQSn, DM, and DQ signals from FPGA core must be connected to theALTDQ_DQS instance. The ALTDQ_DQS instance interfaces to the externalmemory (DDR and DDR2) for these pins.

Read data from the DQ input path should go through a dual-clock FIFO to

transfer the data from the half-rate input block (half-rate resync_clk clockdomain) to the FPGA core clock domain.

Controller has to make sure the write data from core and DQS output pathstrobe must be aligned to ensure that when writing data to external memory,the DQS strobe is center-aligned with the output DQ data to the externalmemory.

f For more information about the timing requirements for the DQS and DQSn strobesignal, DM signal, and DQ data during reading and writing operations, refer to therespective external memory device datasheet.

Create Controller Logic for Address and Command PinsBecause this is a custom external memory interface for DDR and DDR2 interface, youmust design your own custom controller to control the address and command pinsfrom the FPGA core.

Consider the following details when designing the controller for the CKand CK#pins:

DDR2 SDRAM components use CKand CK#signals to clock the address andcommand signals into the memory. Furthermore, the memory uses these clocksignals to generate the DQS signal during a read through the DLL inside thememory. The DDR2 SDRAM data sheet specifies the following timings:

tDQSCKis the skew between the CKor CK#signals and the DDR3 SDRAM-generated DQS signal

tDSHis the DQS falling edge from CKrising edge hold time

tDSSis the DQS falling edge from CKrising edge setup time

tDQSSis the positive DQS latching edge to CKrising edge

tDQSCKis the DQS output access time from CK


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Create Controller Logic for the OCT Calibration Block



The DDR2 SDRAM has a write requirement (tDQSS) that states the positive edge ofthe DQS signal on writes must be 25% ( 90) of the positive edge of the DDR2SDRAM clock input. Therefore, the memory controller should generate the CKandCK#signals using the DDR registers in the IOE to match with the DQS signal andreduce any variations across process, voltage, and temperature. The positive edgeof the DDR2 SDRAM clock, CK, is aligned with the DQS write to satisfy tDQSS.

Consider the following details when designing the controller for theA(address), BA(bank address), CKE, CS#, RAS#, CAS#, WE#, and ODTpins:

1. Address and command signals in DDR2 SDRAM components are clocked into thememory device with the CKor CK#signal. These pins operate at a single data rate(SDR) using only one clock edge. The number of address pins depends on theDDR2 SDRAM device capacity. The address pins are multiplexed, so two clockcycles are required to send the row, column, and bank address. The CS, RAS, CAS,WE, CKE, and ODTpins are DDR2 SDRAM command and control pins. TheDDR2 SDRAM address and command inputs do not have a symmetrical setupand hold time requirement with respect to the DDR2 SDRAM clocks, CK, and CK#.

2. In Stratix III and Stratix IV devices, the address and command clock should beone of the PLL dedicated clock outputs whose phase can be adjusted to meet thesetup and hold requirements of the memory clock. The address and commandclock is also typically half rate, although a full rate implementation can also becreated. The command and address pins use the DDIO output circuitry to launchcommands from either the rising or falling edges of the clock.

3. The chip selects (CS_N), clock enable (CKE), and ODTpins are only enabled for onememory clock cycle and can be launched from either the rising or falling edge ofthe address and command clock signal. The address and other command pins areenabled for two memory clock cycles and can also be launched from either therising or falling edge of the address and command clock signal.

f For more information about the timing requirements for the address and commandpins during reading and writing operations, refer to the respective external memorydevice datasheet.

Create Controller Logic for the OCT Calibration BlockIf calibrated series, parallel, or dynamic termination is used for the I/O in yourdesign, your design requires a calibration block. This block requires a pair of RUPandRDNpins located in a bank that shares the same VCCIOvoltage as your memoryinterface. This calibration block is not required to be in the same bank or side of thedevice as the IOEs it is serving. To use these capabilities in the FPGA, you must use

the ALTOCT megafunction.Consider the following details when designing the memory controller to be used withthe ALTOCT megafunction:

The RUPand RDNinput ports of the ALTOCT instance must be connected to therespective RUPand RDNpins in the FPGA. Note that the RUPand RDNpins are dual-purpose pins and there are multiple pairs of RUPand RDNpins for each bank.


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Instantiate ALTIOBUF Megafunctions



The memory controller controls the calibration_request, s2pload, andcalibration_waitinput ports of this ALTOCT instance, to ensure that thetermination is calibrated based on the PVT (process, voltage and temperature)variation requirements of the custom external memory interface.

The calibration_busyand calibration_shift_busyoutput ports of this

ALTOCT instance must be used by the memory controller to determine when thecalibration process of the termination is complete. This is important, because thenonly normal operations like reading to and writing from and to external memorycan be performed. During termination calibration, the pins interfacing to theexternal memory must not be used for any operations.

The seriesterminationcontroland parallelterminationcontroloutput portsof this ALTOCT instance must be connected to the ser_term_ctrlandpar_term_ctrlinput ports of the ALTIOBUF instance, which interfaces with theexternal memory pins. This is to transfer the calibrated termination settings to theI/O buffers.

f For more information about using these ports in the ALTOCT megafunction, refer toDynamic Calibrated On-Chip Termination (ALTOCT) Megafunction User Guide.

f For more information about implementing calibrated dynamic OCT in your designs,refer toAN 465: Implementing OCT Calibration in Stratix III Devices.

Instantiate ALTIOBUF MegafunctionsAll of the interface pins must be connected to I/O buffers via the ALTIOBUFmegafunction. You must use this megafunction to enable differential capabilities forthe I/O buffer which is connected to a differential DQS pin or to enable dynamic OCTcapabilities for the respective interface pins.

Consider the following details when designing the memory controller to be used withthe ALTIOBUF megafunction:

1. The ser_term_ctrland par_term_ctrlinput ports of this ALTIOBUF instancemust be connected to the respective seriesterminationcontrolandparallelterminationcontroloutput ports of the ALTOCT instance, whichinterfaces with the external memory pins. This is to transfer the calibratedtermination settings to the I/O buffers.

2. The dyn_term_ctrlinput ports of this ALTIOBUF instance must be connected.This port enables Rtduring reads from the DDR and DDR2 external memory, anddisables Rtduring writes from the DDR and DDR2 external memory. This portmust be connected to the output of the dynamic OCT DQ/DQS path in theALTDQ_DQS instance. The input of this path in the ALTDQ_DQS instance shouldbe connected to the memory controller, where it can determine when a read orwrite operation is done.

f For more information about using these ports, refer to I/O Buffer Megafunction(ALTIOBUF) User Guide.

f For more information about implementing calibrated dynamic OCT, refer toAN 465:Implementing OCT Calibration in Stratix III Devic

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