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SINGLE AND DOUBLE PRECISION

FLOATING POINT

MULTIPLICATION AND DIVISION

ALU

Reneesh C Zacharia

Reg. no 2882122

Internal Guide: Mr. T RAVI ME ,(Ph.D )

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GOAL OF THE PROJECT

Implementation of double precision floating

point multiplication and division

Implementation of pc interface of singleprecision floating point multiplication and

division

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INTRODUCTION

The system is a 32-bit floating point ALU.

The system can be expected to perform 32-bit

multiplication and division operations. The system use four levels of pipelining.

The floating point numbers are represented in

IEEE-754 standard.

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REPRESENTATIONREPRESENTATION OFOF FLOATINGFLOATING POINTPOINT

NUMBERSNUMBERS ININ

SINGLE PRECISIONSINGLE PRECISION IEEEIEEE 754754 STANDARDSTANDARD

SIGN EXPONENTIAL MAGNITUDE

22-030-2331

IEEE 754 SINGLE PRECISIONIEEE 754 SINGLE PRECISION

Bits of precision 24

Unbiased exponent Emax 127

Unbiased exponent Emin -126

Exponent bias 127

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REPRESENTATIONREPRESENTATION OFOF FLOATINGFLOATING POINTPOINT NUMBERSNUMBERS ININ

SINGLE PRECISIONSINGLE PRECISION IEEEIEEE 754754 STANDARDSTANDARD

Value = N = (-1)S X 2 E-127 X (1.M)

SIGN EXPONENTIAL MAGNITUDE

22-030-2331

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REPRESENTATIONREPRESENTATION OFOF FLOATINGFLOATING POINTPOINT

NUMBERSNUMBERS ININ

DOUBLE PRECISIONDOUBLE PRECISION IEEEIEEE 754754 STANDARDSTANDARD

SIGN EXPONENTIAL MAGNITUDE

51-062-5263

IEEE 754 DOUBLE PRECISIONIEEE 754 DOUBLE PRECISION

Bits of precision 53

Unbiased exponent Emax 1023

Unbiased exponent Emin -1022

Exponent bias 1023

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REPRESENTATIONREPRESENTATION OFOF FLOATINGFLOATING POINTPOINT NUMBERSNUMBERS ININ

DOUBLEDOUBLE PRECISIONPRECISION IEEEIEEE 754754 STANDARDSTANDARD

Value = N = (-1)S X 2 E-1023X (1.M)

SIGN EXPONENTIAL MAGNITUDE

51-062-5263

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ARITHMETIC UNIT DESIGN

STRUCTURE

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LOGIC UNIT DESIGN STRUCTURE

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ADVANTAGES OF PIPELINING

It can accept a new instruction every clock cycle

The cycle time of the processor is reduced, thus

increasing instruction issue-rate in most cases.

Some combinational circuits such as adders or

multipliers can be made faster by adding morecircuitry. If pipelining is used instead, it can save

circuitry

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DESCRIPTION-DOUBLE PRECISION (64-

BIT)

The 64-bit floating point numbers are stored in four

pipelined registers.

There are four pipelined units. They perform

following functions in parallel.

1. 0 operation number check

2. Exponent addition and subtraction operation

3. Fraction multiplication and division operation4. Result normalization and rounding

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BASICBASIC FLOATINGFLOATING POINTPOINT MULTIPLICATIONMULTIPLICATION

ALGORITHMALGORITHM

Assuming that the operands are already in the IEEE

754 format, performing floating point multiplication:

Result = R = X * Y = (-1)Xs (Xm x 2Xe) *

(-1)Ys (Ym x 2Ye)

involves the following steps:

(1) If one or both operands is equal to zero, returnthe result as zero, otherwise:

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(2) Compute the sign of the result Xs XOR Ys

(3) Compute the mantissa of the result:

Multiply the mantissas: Xm * Ym

Round the result to the allowed number of mantissa bits

(4) Compute the exponent of the result:Result exponent = biased exponent (X) + biased exponent

(Y) - bias

(5) Normalize if needed, by shifting mantissa right,incrementing result exponent.

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MULTIPLICATION FLOW CHART

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BASICBASIC FLOATINGFLOATING POINTPOINT DIVISIONDIVISION

ALGORITHMALGORITHM

Assuming that the operands are already in the IEEE

754 format, performing floating point multiplication:

Result = R = X / Y= (-1)Xs (Xm x 2Xe)/

(-1)Ys (Ym x 2Ye)

involves the following steps:

(1) If the divisor Y is zero return Infinity, if both are zeroreturn NaN

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(2) Compute the sign of the result Xs XOR Ys

(3) Compute the mantissa of the result:

The dividend mantissa is extended to 48 bits by adding 0's to

the right of the least significant bit.

When divided by a 24 bit divisor Ym, a 24 bit quotient is produced.

(4) Compute the exponent of the result:

Result exponent = [biased exponent (X) - biased exponent (Y)]

+ bias

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DIVISION FLOW CHART

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FIRST STAGE OFCONNECTION

GRAPH

OPERAND CHECKING MODULE

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SECOND STAGE

EXPONENT ADDITION AND SUBTRACTION MODULE

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THIRD STAGE

FRACTION MULTIPLICATION AND DIVISION MODULE

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FOURTH STAGE

NORMALIZATIONAND ROUNDING MODULE

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PC INTERFACE

F NCTIONA OC OF PC INTERFACE

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RESULTS-32 BIT

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RESULT-64 BIT

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REFERENCES

Computer Organization by Carl Hamacher

Verilog HDL Samir Palnikar

VLSI Digital Signal ProcessingSystems-Keshab K.parhi

Fundamental of Digital Design Floyed

IEEE Standard of Binary Floating-Point

Arithmetic" IEEEStandard754,IEEE Computer

Society,1985 Design of Double Precision IEEE-754 Floating-Point

Units by Michael Kennedy B.I.T -Griffith University

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THANK YOU