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8259A PRIORITY INTERRUPT CONTROLLER

The priority interrupt controller is used when several I/O devices transfer data using interruptand they are to be connected to the same interrupt level of the Microprocessor. When the number of theI/Odevices is less than the number of interrupt levels of the Microprocessor, such controllers are notrequired.

The Intel 8259 is a single chip priority interrupt controller. It is a 28 pin DIP (Dual InlinePackage) I.C. and uses N-MOS technology.

8259 programmable Interrupt controller handles up to eight vectored priority interrupts for the CPU. Itis cascadable for up to 64 vectored priority interrupts without additional circuitry.

INTERNAL BUS

IR0

IR1

IR2

IR3

IR4IR5

IR6

IR7

CAS0

CAS1

CAS2

SP/EN

RD

WR

A0

CS

D7D0

CONTROL LOGIC

In

Service

Reg(ISR)

Priority

Resolver

Interrupt

requestregister

Interrupt Mask REG

DATA

BUS

BUFFER

READ/

WRITE

LOGIC

CASCADE

BUFFER/

COMPARA

TOR

INTA INT

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CS: (Chip select) : The low status of this signal enables communication between CPU and 8259.WR: 0Enables Intel 8259 to accept command word from CPU.

RD : 0On this pin enables Intel 8259 to send the various status signal on the data bus for CPU.

D0D7 :Bi-directional data bus. Control status and interrupt vector informations are transferred via

this bus.

CAS0CAS2:Cascade lines.

SP / EN :Slave program / Enable buffer.

INT:Interrupt. It is used to interrupt the CPU.

INTA:Interrupt acknowledge.

IR0IR7: Interrupt requests. I/O devices send interrupt request through these lines.

A0 :Address line. It acts in conjunction with RD,WR, and CS. The Intel 8259 uses it to interruptcommand words, the CPU writes and status the CPU wants to read.

FigB: Interfacing of 8259 and I/O devices

INTR

INT

INTEL 8085/86

RAM

ROM

Output

Device

OutputDevice

INTEL

8259

Input

Device

Input

Device

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Fig B shows the connections of PIC (programmable Interrupt Controller) and I/O devices tothe Microprocessor. The priority can be assigned to the I/O devices connected to PIC. 8 I/O devicescan be connected to 8259 through IR0IR7lines.

8259 accepts requests from I/O devices and determines which of the incoming request is ofhighest priority. After checking the priority of the interrupt request, the 8259 sends an interrupt signalto the Microprocessor through INT line. The Microprocessor sends acknowledge signal through INTAline. On receiving INTA signal all interrupts of lower priority are inhibited (hold back) and the 8259sends a CALL instruction to the Microprocessor. The CALL instruction is unique so that theMicroprocessor can take up the ISS(Interrupt Service Subroutine) for the I/O device which hasrequested for data transfer.

Interrupt Operation:

To implement interrupts, the interrupt enable flip-flop in the Microprocessor should be enabledby writing the EI instruction, and the 8259 should be initialized by writing control words in the controlregister. 8259 requires two types of control words:

Initialization command words (ICWs) andOperational Command Words (OCWs).

The ICWs are used to setup the proper conditions and specify RST vector addresses. TheOCWs are used to perform functions such as masking interrupts, setting up status, read operations

etc.,.

After 8259 is initialized, the following sequence of events occurs when one or more interrupt requestlines go high.

1. The interrupt request register stores the requests.2. The priority counter checks three registers:

IRR for interrupt requestsThe IMR for masking bits andISR for interrupt request being served. It resolves priority and sets the INT high

3. The Microprocessor acknowledges the interrupt by sending INTA.4.

After INTA is received, the appropriate priority bit in the ISR is set to indicate which

interrupt level is being served , and the corresponding bit in the IRR is reset to indicate thatthe request is accepted. Then the OP-code for call instruction is placed on the data bus.

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8259 PIC

Fully nested mode: This is a general purpose mode in which all IRs are arranged from highest tolowest, with IR0as highest and IR7as the lowest.

In addition, any IR can be assigned the highest priority in this mode. The priority sequence willthen begin at that IR

IR0 IR1 IR2 --------------------- IR70 1 2 --------------------- 7

Automatic Rotation mode: A device after being served, receives the lowest priority. Assumingthat the IR2has just been serviced. It will receive the seventh priority.

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR75 6 7 0 1 2 3 4

Specific Rotation Mode: This mode is similar to automatic rotation mode, except that the usercan select any IR for the lowest priority. Thus fixing all other priorities. 8259 is a complex device withvarious modes of operations.

Interrupt Triggering:8259 can accept an interrupt request with either the edge triggered mode

or the leveltriggered mode. This mode is determined by the initialization instructions.

Interrupt status: The status of the interrupt requests (IRR,ISR and IMR) can be read and thisstatus information can be used to make the interrupt process versatile.

Poll method:The 8259 can be setup to function in a polled environment. The MPU polls the 8259rather than each peripheral.

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Programming 8259:The 8259 requires two bytes of command words. Initialization CommandWords (ICWs), Operational Command Words (OCWs). 8259 can be initialized with four ICWs. The

first two are essential and the other two are optional, based on the modes being used. Once initialized8259 can be setup to operate in various modes by using three different operational command words.

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 A7 A6 A5 1 LTIM ADI SNGL IC4

1 ICW4needed

0 notneededSNGL - 1 - single

0

- cascade mode

ADI -- Call Address Interval1 -- interval of 4

0 -- interval of 8

LTIM -- 1 -- Level Triggered Mode0 -- Edge Triggered Mode

A5A7 -- Of interrupt vector address.

ICW2

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 A15 A14 A13 A12 A11 A10 A9 A8

It is the interrupt vector address

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IR INTERVAL 4D7 D6 D5 D4 D3 D2 D1 D0

7 A7 A6 A5 1 1 1 0 06 A7 A6 A5 1 1 0 0 05 A7 A6 A5 1 0 1 0 04 A7 A6 A5 1 0 0 0 03 A7 A6 A5 0 1 1 0 02 A7 A6 A5 0 1 0 0 0

1 A7 A6 A5 0 0 1 0 00 A7 A6 A5 0 0 0 0 0

IR INTERVAL 8D7 D6 D5 D4 D3 D2 D1 D0

7 A7 A6 1 1 1 0 0 06 A7 A6 1 1 0 0 0 05 A7 A6 1 0 1 0 0 0

4 A7 A6 1 0 0 0 0 03 A7 A6 0 1 1 0 0 02 A7 A6 0 1 0 0 0 01 A7 A6 0 0 1 0 0 00 A7 A6 0 0 0 0 0 0

IR0

IR1

IR2

IR3

IR4

IR5

IR6

A7

A6

A5

MSB

A3

A2

A1LSB

3 TO 8

DECODER8259

CS

A0

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Fig shows an interrupt driven system 8257. Four sources are connected to IR lines of 8259,emergency signal, A/D converter, keyboard and printer of these emergency signal has highest priorityand produces has lowest priority. Explain the following initialization instructions.

D1 Initialization InstructionsMV1 A,76H ICW1OUT 80H Initialize 8259A

MV1 A, 20H ICW2OUT 81H Initialize 8259

1. The DI instruction disables the interrupts. So that the initialization process will not be interrupted.2. The command word 76H specifies the following parameters.

A0 D7 D6 D5 D4 D3 D2 D1 D0


0 0 1 1 1 0 1 1 0

Address lines A0A4 will be supplied by 8259

D0 indicates NO ICW$ is needed.D1 indicates single 8259 is used.D2 call address interval is 4 locationsD3 edge triggered modeD5D7 are address lines A5A7

A7 A6 A5 A4 A3 A2 A1 A0

0 1 1 0 0 0 0 0

The address bits A0A4are supplied by 8259. The subsequent addresses are four locations a part leg.IR1= 64IR0has the highest priority. The low order byte of IR0call address.

D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 0 0 0 0 0

0 1 1

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A0A4are supplied by 8259 and A5A7are supplied by ICW1

0 1 1 0 0 0 0 06 0

The low order byte of IR0call address is 60H.3.

The port address of 8259 for ICW1is 80H. A0should be at logic 0 and the other bits are determinedthe decoder

4. Command word ICW2is 20H, which specifies the high order byte of the call address.

D7 D6 D5 D4 D3 D2 D1 D0

A15 A14 A13 A12 A11 A10 A9 A8

0 0 1 0 0 0 0 0

5. The port address of ICW2 is 81H. A0should by at logic 1.

The low order byte of IR0call address is 60H.IR1 64HIR2 68H.IR6 78H

From ICW1 8259

0 1 1 1 1 0 0 0

The RST code for IR0 2060IR1 2064IR2 2068.IR6 2078

Port addresses for command Words ICW1 80ICW2 81ICW3 82

ICW4 83

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INITIALISING AN 8259:

The base address for the 8259A is FFOOh. For an 8259 the two internal addresses are selected by ahigh or a low on the Ao pin.The two system addresses of 8259A are

FFOOHFFO2H

ICW'S are needed for various 8259 applications Fig shows this in flowchart form. According to this an ICW1and ICW2 must be sent to any 8259 in the system. If the system has any slave 8259 (cascade mode)then anICW3 must be sent to the master and a different ICW3 must be sent to the slave..If the system is an 8086 or of you want to specify certain special conditions, then you have to send an ICW4 tothe master and to each slave. Now let us look at the formats for the different ICW'S.

The first thing to notice about the ICW formats in fig is that the bit Ao on the left end of each of these isnot part of the actual command word. This bit tells you the internal address that the control word must be sentto. The Ao = O next to ICW1 tells you that ICW1 must be sent to internal address O, which for our 8259Acorresponds to system address FFOOH.

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ICW1

In

CascadeMode

Is ICW4Needed

ICW3

ICW4

No

IC4 = 0

No

SNGL = 1

YesSNGL = 0

Yes IC4 = 1

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8259A initialization command word formats sending order.

A0 D7 D6 D5 D4 D3 D2 D1 D0


The A0 in the left end of each of the command word is not part or actual command word.

This bit tells you the internal address that the control word must be sent to.If Ao=0 The command word corresponds to the system address FFOOH.If A0=1 The command word corresponds to the system address FFO2H

DO: The least significant bit of ICW1 tells the 8259 whether it needs to look for an ICW4 or not. Since we areusing the device in an 8086 system, we need to send ICW4. Therefore we make bit Do a 1.D1: 1-single 8259 is used

0 -cascade mode.D2: Is a don't care, so we make it a D.

D3: 1-level triggered mode0-edge triggered mode.

We usually use edge-triggered mode.

D5 / D6 / D7: are don't cares.So we make them O's.

I C W 2Ao D7 D6 D5 D4 D3 D2 D1 D0

1 A15 A14 A13 A12 A11 A10 A9 A8

ICW2is used to tall the 8259 the type number to send in response to an interrupt signal on the IRO input inresponse to an interrupt signal on same other IR input, the 8259 will automatically add the number of the IRinput to this base number and send the result to the 8086 as the type number for that input.

Interrupt types O-31 are dedicated / reserved type 32-is the lowest type number available highest.

ICW2Ready to acceptinterru t re uests

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ICW3(Master Device):Ao D7 D6 D5 D4 D3 D2 D1 D0

1 S7 S6 S5 S4 S3 S2 S1 S0

1 - IR input has a slaveO - IR input does not have a slave

ICW3(Slave Device):Ao D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 ID2 ID1 ID0

ID2 ID1 ID0 Slave ID

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

If we are not using a slave we need not send ICW3.

If we are using a slave 8259 in a system, we have to send an ICW3 to the master to tell it which IR inputs haveslaves.

You have to send an ICW3 to a slave 8259 to give it an ID number. The ID number you give a slave is equal tothe IR input of the master.

ICW4

Ao D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 SFNM BUF M/S AEOI PM

DO = 1 - 8086 Mode O - 8085 ModeD1 = 1 - Auto EOI O - Normal EOI

D4: 1 - Special fully nested mode

0 - Not special fully nested mode

Because we are operating on 8086 we have to send an ICW4.If the automatic end of interrupt bit is set in ICW4 the 8259 will automatically reset the in-service register bitfor the interrupt input that is being responded to when the second interrupt acknowledge pulse is received.

OCW'S

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In addition to the initialization command words 8259 has a second set of command words calledoperational command words.

OCW1: A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0

Interrupt Mask

1

- Mask Set0 - Mask Reset

An OCW1 must be sent to an 8259 to unmask any IR input that you want it to respond to.For example let's assume that we want to use only IR2 and IR3.

0-unmask1-mask.

OCW1 A0 D7 D6 D5 D4 D3 D2 D1 D01 1 1 1 1 0 0 1 1

OCW2 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 R SL EOI 0 0 L2 L1 L0

L2 L1 L0 IR Level to beacted upon

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 51 1 0 6

1 1 1 7

OCW2 is used to reset a bit in the in-service register. This is usually done at the end of the interrupt serviceprocedure. But it can be done at any time in the procedure.Once the bit in ISR is reset the 8259 can respond to interrupt signal of lower priority.In small systems we usually use the non-specific end of interrupt command word.OCW2 is used is used to tell 8259 to rotate the priorities of the IR inputs so that after an IR input is serviced, itdrops to the lowest priority.

OCW3 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 ESMM SMM 0 1 P RR RIS

D0, D1- Read Register CommandD2 - 1 - Poll command

0 - No poll commandD5, D6 - Special Mask Mode

SOFTWARE INTERRUPT APPLICATIONS

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The 8086 Software Interrupt Instruction INT N can be used to test any type of interrupt procedure. Forexample to test a type 64 interrupt procedure without the need for external hardware you can just execute theinstruction INT 64.

Another important use of software interrupts is to call basis input output system, or BIOS, procedures inan IBM-PC type computer these procedures in the system rolls perform specific input or output functions, suchas reading a character from the keyboard, working some characters to the CRT, or reading some information

from a disk.

INT 17h instruction can be used to call a procedure which sends some characters to the printer.

MOV AX, 4C00HInt 21h Graceful exit to DOS with function call 4CH

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