Upload
ngonhi
View
216
Download
0
Embed Size (px)
Citation preview
DFT MethodologyDFT Methodologyfor Power Issues
during Production Test
Beom Ik, [email protected]
Nov. 15, 2008
Design Technology TeamSystem LSI, Samsung Electronics
2008 Test Workshop
ContentsContents
IntroductionPower aware DFT DesignPower-aware DFT DesignPower-Aware ATPGDFT Implementation FlowReferences
[1]2008 Test Workshop
Test Issues for SOC Devices with Large SizeTest Issues for SOC Devices with Large Size
Test CostTest TimeTest TimeTest Data Volume
Qualityfunction
QualityDefect PPMF lt M d l
function
SFFSFFSFFSFFCLK1
Fault Model
Yield f nction
SFFSFFSFFSFFCLK2
OverkillYield Loss due to Power
function
SFFSFFSFFSFFCLK3
during Production Test
[2]2008 Test Workshop
Power-aware Test ChallengePower-aware Test Challenge
Power-aware DFT DesignDFT Design w/o Power Design ATEDFT Design w/o Power DesignPower Reduction during Test
Power Design and AnalysisPower Design and AnalysisSi OverheadStatic Power Analysis Power
SupplyyDynamic Power Analysis
Solutions for Power-aware DFT
pp y
DFT DesignPower Scheduling
DataPads
Power Management ATPG
Low Power Budget
[3]2008 Test Workshop
Low Power BudgetPowerPads Device under Test
Power Reduction for Scan Test ModePower Reduction for Scan Test Mode
Design ModificationScan Chain OrderingScan Chain OrderingGating BlockingDesign Partitioning functionDesign Partitioning
Test Pattern GenerationT t P tt M difi ti f i
SFFSFFSFFSFFCLK1
Test Pattern ModificationTest Pattern CompressionT P O d i
function
SFFSFFSFFSFFCLK2
Test Pattern OrderingPower-aware ATPG
function
SFFSFFSFFSFFCLK3CLK3
[4]2008 Test Workshop
Test Power EstimationTest Power Estimation
WSA (Weighted Switching Activities)S1: Constraints at Each NodeS1: Constraints at Each Node
Toggles at Each NodeNo of Fan-out of Each Node
S2: Constraints at Each Flip-FlopToggles at Each Flip-Flop
S3: Constraints at Each Flip-FlopToggles at Each Flip-FlopFan-out Cone Size of Each Flip-Flop
[5]2008 Test Workshop
ContentsContents
IntroductionPower aware DFT DesignPower-aware DFT DesignPower-Aware ATPGDFT Implementation FlowReferences
[6]2008 Test Workshop
Power-aware Scan Chain OrderingPower-aware Scan Chain Ordering
Power-aware Scan Chain Ordering
functionV1 = 0 1 1 0 R1= 0 1 0 0V2 = 0 1 0 1 R1= 1 0 0 0V3 = 0 1 1 1 R1= 1 0 1 1
SFFSFFSFFSFF
Weight Transitions = Σ (Size of Scan Chain Position Transition)Weight Transitions Σ (Size of Scan Chain Position Transition)
[7]2008 Test Workshop
Power/Routing-aware Scan Chain OrderingPower/Routing-aware Scan Chain Ordering
Scan Chain Ordering with Routing ConstraintsClusteringClusteringPower-driven Scan Cell Reordering after ATPGCluster Ordering
RTL
Cluster Ordering
DrawbacksSynthesis
Scan Design
ATPG
P & R
ATPG
[8]2008 Test Workshop
Gate BlockingGate Blocking
Power Reduction during Shift ModeFF Output Signal DisableFF Output Signal DisableFF with Low Activity
DrawbacksDrawbacks
function
SFFSFFSFFSFF
[9]2008 Test Workshop
Design PartitioningDesign Partitioning
Design Partition with Clock GatingHow to partition the device?How to partition the device?
Test TimeFault Coverage
functiong
Drawbacksfunction
SFFSFFSFFSFFCLK1
function
SFFSFFSFFSFF
function
CLK2
SFFSFFSFFSFFCLK3
[10]2008 Test Workshop
Design PartitioningDesign Partitioning
Design Partition with Multiple Scan Enable SignalsHow to partition the device?How to partition the device?
Test TimeFault Coverageg
Drawbacks
[KBU]
[11]2008 Test Workshop
Design PartitioningDesign Partitioning
MD-SCAN (multi-duty scan)How to decide the duty depth?How to decide the duty depth?Different clock for shift and capture mode
Drawbacksfunction
Drawbacks
function
SFFSFFSFFSFFCLK1
CLK1
10
CK1
CK
function
SFFSFFSFFSFFCLK2
CLK1
CLK210
CK2
CK
function
SFFSFFSFFSFFCLK3
CLK3
10
CK3
CK
[12]2008 Test Workshop
ContentsContents
IntroductionPower aware DFT DesignPower-aware DFT DesignPower-Aware ATPGDFT Implementation FlowReferences
[13]2008 Test Workshop
Test Pattern ModificationTest Pattern Modification
Random X-FillingDynamic compaction for detecting more faultsDynamic compaction for detecting more faults
Non-Random X-Filling0 Filli0-Filling1-FillingAdj t X Filli
function
Adjacent X- Filling
function
SFFSFFSFFSFFCLK1
function
SFFSFFSFFSFFCLK2
function
SFFSFFSFFSFFCLK3
[14]2008 Test Workshop
X 1 X X X 0 X X X X X 1
Test Pattern ModificationTest Pattern Modification
LCP (Capture Power Reduction) X-FillingIssuesIssues
Target Selection ProblemValue Selection Problem
Methods0-Filling, 1-Filling, Minimum-Transition-Filling
w/o considering the Impact of Capture PowerX-Filling for Reduction of Logic Transition Count at Scan FF
outputsoutputs. No Correlation with total Capture Power and Scan FF
TransitionX 1 X X X 0 X X X X X 1
(1) target selection(2) value selection (0/1)
[15]2008 Test Workshop
(2) value selection (0/1)
LCP X-FillingLCP X-Filling
LCP X-FillingX-Score for X-Filling Target SelectionX Score for X Filling Target SelectionProbabilistic Weighted Capture Transition Count for X-
Filling Value SelectionFilling Value SelectionThe probabilistically-estimated number of weighted capture
transitions at all nodes (gates and FFs)Weight:
Toggles Fan out cone sizeFan-out cone size
weighted capture transition count: (G1 G3 ff1)
[16]2008 Test Workshop
weighted capture transition count: (G1, G3, ff1)WCT(v1) = 1*1 + 1*1 + 1*2 = 4
Test Pattern ModificationTest Pattern Modification
Test Pattern Modification with Bit-Stripping
function
SFFSFFSFFSFF
0이나 1로검출되는불량이서로동일함.
[17]2008 Test Workshop
Test Pattern CompressionTest Pattern Compression
Static Compaction considering Power DissipationConstraint WSA (Weighted Switching Activities)Constraint WSA (Weighted Switching Activities)
V1 = X 0 X 0 X 0 XV1 X 0 X 0 X 0 XV2 = 1 X 1 X 1 X 1
(6 Transition)
V0 = 1 0 1 0 1 0 1
[18]2008 Test Workshop
Power-aware ATPGPower-aware ATPG
Low Power for Capture Mode
Conventional ATPG
WSA Max. allowedThreshold
Vectors with High Capture Power (Tv)is replaced with new
V tVectors(low capture power)
Fault List Generation for Tv
Capture-power aware ATPG
[19]2008 Test Workshop
ContentsContents
IntroductionPower aware DFT DesignPower-aware DFT DesignPower-Aware ATPGDFT Implementation FlowReferences
[20]2008 Test Workshop
Power-Aware Scan Design & ATPG FlowPower-Aware Scan Design & ATPG Flow
Scan Design
Power-ware ATPGConventional ATPG Conventional ATPG
Remove ATPG patternwith high Switch Activity
Vect
or f
requ
ency
g y
Power-aware ATPG
Switching ActivityV
[21]2008 Test Workshop
power-critical patterns
Power-Aware Scan Design & ATPG FlowPower-Aware Scan Design & ATPG Flow
Scan Design
Power-aware ATPG
Power-ware ATPG
Remove ATPG patternwith high Switch Activity
Conventional ATPG
eque
ncy
g y
Conventional ATPG
Vect
or f
re
[22]2008 Test Workshop
Switching Activity
Power-Aware Scan Design & ATPG FlowPower-Aware Scan Design & ATPG Flow
Power-aware Scan Design
Power-aware ATPGPower-ware ATPG Conventional ATPG
Remove ATPG patternwith high Switch Activity
uenc
y
Conventional ATPG
Vect
or f
req
Correlation with Shmoo
Switching Activity
power-critical patternspatterns
Power-aware ATPGWith d i t i t
[23]2008 Test Workshop
With design constraints
Power-Aware Scan Design & ATPG FlowPower-Aware Scan Design & ATPG Flow
Power-aware Scan Design
Power-aware ATPG
Remove ATPG patternwith high Switch Activity
Power-ware ATPG Conventional ATPG
with high Switch Activity
Conventional ATPG
Correlation with Shmoo
Vect
or f
requ
ency
Correlation with Shmoo
Power-aware ATPG
[24]2008 Test Workshop
Switching Activity
power-critical patterns
With design constraints
ATPG & Power Issues with MemoriesATPG & Power Issues with Memories
Power issue of memories for ATPGATPG w/ memoriesATPG w/ memories
AlgorithmTest time
D QTITECK
functionD QTITE
Fault coveragetest quality
10 function
D QTITECK
SRAM
CSNWEN
10
TECK
ATPG w/o memoriesmemories: black box
i di bl d
D QTITECK
OWNDI
memories are disabled
BISTBIST
compareExpected
data Pass/Fail
[25]2008 Test Workshop
Example of Power-Aware Scan Design & ATPG Flow
Example of Power-Aware Scan Design & ATPG Flow
Scan Design Rule Check (1)
RTL Code
ATPG with
X-FillingBit-Stripping
Static CompressionPower-aware ATPG
Fault Coverage Estimation (2)
Synthesis (3)
Switch Activity Budget (5)
Remove ATPG pattern with high FF Switch Activity (6)
Enough FC? (7)yes
WSA
Power-aware Scan Design with Scan Compression (4) ATPG with
Switch Activity Budgetand design partitioning (8)
Remove ATPG pattern with
yesno
High Fault Coveragewith Low Overhead
Conventional ATPG (11)
emo e G pattern w th high FF Switch Activity (9)
Enough FC? (10)yes
no
( )
Finished (12)
Scan Chain OrderingGating Blocking
Design Partitioning
Shmoo Analysis (13)
Remove ATPG patternwith power issue (14)
Add test patterns
Si Correlationwith Shmoo
[26]2008 Test Workshop
Add test patternsfor target faults (15)
ContentsContents
IntroductionPower aware DFT DesignPower-aware DFT DesignPower-Aware ATPGDFT Implementation FlowReferences
[27]2008 Test Workshop
ReferencesReferences
[1] D. Berthelot,et al., "An Efficient Linear-Time Algorithm for Scan Chain Optimization and Repartitioning”, ITC 2002.
[2] F. Corno et al., "Test Pattern Generation Methodology for Low Power Consumption", VTS 1998.gy p
[3] J. Saxena,et al., "An Analysis of Power Reduction Techniques in Scan Testing", ITC 2001
[4] L. Guiller, et al., "Integrating DFT in the Physical Synthesis Flow”, ITC 2002.
[5] K. M. Butler, et al., "Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT[5] K. M. Butler, et al., Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques,” ITC 2004.
[6] Meng-Fan Wu, et al., "An Efficient Peak Power Reduction Technique for Scan Testing", IEEE ATS 2007,
[7] M. Hirech, et al., "A New Approach to Scan Chain Reordering Using Physical Design Information”, ITC 1998.
[8] P. Girard, et al., "Reducing Power Consumption during Test Application by Test Vector Ordering ”, IEEE Int Symp on Circuits and Systems 1998IEEE Int. Symp. on Circuits and Systems, 1998
[9] R. Sankaralingam, et al., "Controlling Peak Power During Scan Testing", VTS 2002.
[10] R. Sankaralingam, et al., "Static Compaction Techniques to Control Scan Vector Power Dissipation", VTS 2000.
[11] S. Bhunia, et al., "Low-Power Scan Design Using First-Level Supply Gating", IEEE Transactions on VLSI, 2005
[12] S. Gerstendoerfer, et al., "Minimized Power Consumption for Scan-Based BIST", ITC 1999
[28]2008 Test Workshop
ReferencesReferences
[13] S. Kajihara, et al., "Test Vector Modification for Power Reduction during Scan Testing", VTS 2002[14] S. Makar, et al., "A Layout-Based Approach for Ordering Scan Chain Flip-flops”, ITC 1998.[15] S. Remersaro, et al., "Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based
Designs" ITC 2006Designs", ITC 2006[16] J. Saxena, et al., "An Analysis of Power Reduction Techniques in Scan Testing". ITC, 2001.[17] S. Ravi, et al, “Methodology for Low Power Test Pattern Generation Using Activity Threshold Control
Logic”, ICCAD, Nov 2007.[18] S.Wang, et al., "An Automatic Test Pattern Generator for Minimizing Switching Activity During Scan
Testing Activity", IEEE Transactions on CAD 2002.[19] T. Yoshida, et al., "MD-Scan Method for Low Power Scan Testing", ATS 2002.[20] V. Dabholkar, et al., "Techniques for Reducing Power Dissipation During Test Application in Full Scan [ 0] ab o a , et a , ec ques o educ g o e ss pat o u g est pp cat o u Sca
Circuits", IEEE Transactions on CAD, 1998[21] X. Wen, et al., "On Low-Capture-Power Test Generation for Scan Testing", VTS 2005[22] X. Wen, et al., "A New ATPG Method for Efficient Capture Power Reduction During Scan Testing", VTS
2006[23] Xiaoqing Wen, et al., "A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test
Generation”ICCD 2006. [24] Y. Bonhomme et al., "Efficient scan chain design for power minimization during scan testing under
routing constraint", ITC 2003.g ,[25] Y. Bonhomme, et al., "Power Driven Chaining of Flip-flops in Scan Architectures”, ITC 2002.
[29]2008 Test Workshop