EE361-SingleMIPS

1

Galen Sasaki EE 361 University of Hawaii 1

Single Cycle Processor

This processor takes exactly ONE clock period to execute an instruction.

We’ll design it in stages, from very simple to more complicated:

1. Executes only add $1,$2,$32. Executes add $r1,$r2,$r3, where $r1,$r2,$r3 are any registers3. Executes any arithmetic R-Type instruction4. Executes sw5. Executes lw6. Executes j7. Executes beq

Design approach: What do the instructions do? Implement hardware.


Single Cycle MIPS: Whoa

Shift�left 2

PC

Instruction�memory

Read�address

Instruction�[31– 0]

Data�memory

Read�data

Write�data

RegistersWrite�register

Write�data

Read�data 1

Read�data 2

Read�register 1

Read�register 2

Instruction [15– 11]



Add

ALU�result

Zero


MemtoRegALUOpMemWrite

RegWrite

MemReadBranchJumpRegDst

ALUSrc


4

M�u�x

Instruction [25– 0] Jump address [31– 0]

PC+4 [31– 28]

Sign�extend

16 32Instruction [15– 0]

1

M�u�x

1

0

M�u�x

0

1

M�u�x

0

1

ALU�control

Control

Add ALU�result

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0

1 0

ALU

Shift�left 226 28

Address

2


Machine 1: Only add $1,$2,$3

Reg 2

Reg 3

Reg 1

Adder

Registers are a bank of 32 D flip flops (clock not shown)

Adder takes two 32-bit numbers and outputs thesum of 32-bits.

The registers have different functions:Registers 2 and 3 hold their values,

and are read fromRegister 1 is written to


New RegisterAnother Register with Load control:

It loads if Load = 1, and holds if Load = 0

Register

Input

Output

Load Clock

An implementation of 1-bit register

D flipflopMUX

InputOutput

ClockLoad

01

Multiplexer (MUX)Output = Input 0 if Select = 0Output = Input 1 if Select = 1

// 3-bit registermodule Reg3(in,out,load,clock);

input [2:0] in;input load, clock;output [2:0] out;reg [2:0] out;

always @(posedge clock)beginif (load == 1) out = in;end

endmodule

3


MultiplexerMUX

012

3

Select

Typically an “n:1 multiplexer” has n inputsand one output, where n is a power of 2.

It’s a combinational circuit.

Function: Output = Input k, if select = k, (k = 0, 1, 2, ...)

// 4:1 multiplexermodule Mux4(in0, in1, in2, in3, select, out);

input [31:0] in0, in1, in2, in3;input [1:0] select;output [31:0] out;reg [31:0] out;

always @(in0 or in1 or in2 or in3 or select)case (select)

0: out = in0;1: out = in1;2: out = in2;3: out = in3;

endcaseendmodule


New “add $1,$2,$3” Processor

Reg 2

Reg 3

Reg 1

Adder

load

load

load

0

0

1

Step 1. Get the register values

Step 2. Add the values

Step 3. Store the sum

4


Machine 2: add $r1,$r2,$r3

• Add any registers• New parts

– Instruction memory (stores programs)– Program counter (PC)– Register file

• Multiplexer• Demultiplexer


add $r1, $r2, $r3

InstructionMemory

PC

+

program counter

0 r2 r3 r1 0 32 $r2 $r3 $r1

Register filePC isincrementedby 4 everyclock cycle

5


Instruction MemoryTo simplify the discussion, let’s suppose

The memory is ROM32-bits wide1024 memory words (instructions)

Instruction Memory

PCinstr[31:0]

\\ Example Instruction Memorymodule InstrMemory(addr,instr);

input [31:0] addr;output [31:0] instr;reg [31:0] instr;

always @(addr[11:2]);case(addr[11:2])

0: instr={6’d0,5’d’2,5’d3,5’d1,5’d0,6’d32};1: instr={6’d0,5’d’5,5’d6,5’d4,5’d0,6’d32};2: instr={6’d0,5’d’8,5’d9,5’d7,5’d0,6’d32};3:

.

.endcase

endmodule

Address Contents Instruction0 0 2 3 1 0 32 add $1,$2,$34 0 5 6 4 0 32 add $4,$5,$68 0 8 9 7 0 32 add $7,$8,$912 0 11 12 10 0 32 add $10,$11,$12


Register File

$0

$1$2

$3Store Read

RegStore(Input)

Read(Output)

clockload

Register file

clockload

How do we select registerswhich one read from

and which to write to?

6


Register File

$0

$1$2

$3

Writedata

Readdata

Register file

clockload

Writeaddr

Readaddr

Devices to select things

Multiplexer (MUX)

Demultiplexer (DMUX orDEMUX)

DMUX

input

Y0

Y1

Y2

Y3

select

Yk = input, if select = k0, otherwise


Register File

Writedata

Clock not shown but it’s tied to all registers

WriteAddr

(select)

$0

$1

$2

$3

Writing to a registerload

load

load

load

DMUX

0

1

2

3

load

$0

$1

$2

$3

Readdata

ReadAddr

(select)

MUX

0

1

2

3

Reading from a register

7


Register File for MIPS

Register File$0,$1,.., $31

$r2 addr (r2)

$r3 addr (r3)

$r2 data

$r3 data

$r1 addr (r1) $r1 data

Clock Write (load)

Write = 1 causes register $r1 to load at the next clock transition.Otherwise, no registers load.

add $r1,$r2,$r3

5 bits wide 32 bits wide

A register file is an array of registers that can be accessedby providing the addresses of the registers to be accessed.


Register File $r2 addr

$r3 addr

$r2 data

$r3 data

$r1 addr

$r1 data

write

Clock is not shown, but it’sconnected to all registers

Register 0

Register 1

Register 2

Register 31

MUX

MUX

DMUX

load

Demultiplexer function:Output k = input, if select = kAll other outputs are 0

012

31

8


Verilog// Register filemodule RegisterFile(writeaddr,writedata,readaddr1,readdata1,readaddr2,readdata2,write,clock);

input [4:0] writeaddr, readaddr1, readaddr2;input [31:0] writedata;input write,clock;output [31:0] readdata1,readdata2;

reg [31:0] RegCell [0:31];

always @(posedge clock) beginif (write == 1) RegCell[writeaddr] = writedata;end

assign readdata1 = RegCell[readaddr1];assign readdata2 = RegCell[readaddr2];

endmodule

RegisterFile

write

writeaddr writedata

readaddr1

readaddr2

readdata1

readdata2


VerilogHow do we deal with $0 = 0?

The statement

assign readdata1 = RegCell[readaddr1];

should be changed to

always @(readdr1 or RegCell[readaddr1])beginif (readaddr1 == 0) readdata1 = 0;else readdata1 = RegCell[readaddr1];end

9


add $r1, $r2, $r3

InstructionMemory

PC+4 Register

File$0-$31

+

program counter(32-bit register,always loading)

Step 1. Fetch Inststruction

Step 2. Get $r2 and $r3

Step 3. Add $r2 and $r3

Step 4. Store sum.

Step 4. Update PC

0 r2 r3 r1 0 32

r2r3r1


Machine 3: Arithmetic R-TypeArithmetic R-Type Instructions: add, sub, or, and, and slt. or and and are bitwise logic operations.

InstructionMemory

PC+

4

RegisterFile ALU

$r2

$r3

operation $r1,$r2,$r3

Controllerfunct field

r2r3r1

RegWrite

result

ALU is a combinational circuit that is the calculator for the CPU

0 r2 r3 r1 0 functStep 1.Fetch Instr.

Step 2.Access reg. values.Select ALU

Step 3.ALU computesresult

Step 4.Store resultUpdate PC

1

10


Arithmetic Logic Unit (ALU)Function TableALU ControlInput Function000 AND001 OR010 add110 subtract111 set on less than

AND slt

subaddOR

A B

result

ControlInput(select)



AND sltsubaddOR

A B

result

ControlInput(select)

MUX0 1 2 6 7

We’ll do a more detailed design of this laterin the semester.

11



// ALU modulemodule ALU(a,b,result,select);

input [31:0] a, b;input [2:0] select;output [31:0] result;reg [31:0] result;

always @(a or b or select)begincase (select)

0: result = a & b;1: result = a | b;2; result = a + b;6: result = a - b;7: result = (a-b)>>31;default: result = 0;

endcaseendmodule


Controller ALU Function TableALU ControlInput Function000 AND001 OR010 add110 subtract111 set on less than

R-Type Instruction Function FieldInstruction Function Fieldadd 32sub 34and 36or 37slt 42

ConrollerInstructionfunct field ALU

Controller Truth TableInput Output000000 xxx000001 xxx

100000 [32]100001 [33]100010 [34]100011 [35]100100 [36]100101 [37]

101010 [42]

12


Machine 4: swstore word: sw $r1,const($r2)

InstructionMemory

PC

DataMemory

data in

address

43 r2 r1 const

$r1$r2

+ALU

sign ext

data

RAM

Register File


Random Access Memory (RAM)

RAM

Very much like a register file only bigger, much bigger.

Address DataOut

DataIn

Writeclock

Write = 1 --> RAM[Address] = DataInWrite = 0 --> hold

DataOut = RAM[Address]

// module for RAMmodule RAM(address,dataout,datain,write,

clock);input [9:0] address;input [31:0] datain;input write,clock;output [31:0] dataout;reg [31:0] dataout;reg [31:0] Mem[0:1023];

always @(posedge clock) if (write==1) Mem[address] = datain;

always @(Mem[address]) dataout = Mem[address];

endmodule

13


Machine 4: swstore word: sw $r1,const($r2) 43 r2 r1 constArithmetic R-Type Instructions: oper $r1,$r2,$r3 0 r2 r3 r1 0 funct

InstructionMemory

PC+

4

RegisterFile ALU

$r2

$r1

Controlleropcode, funct field

r2r1

RegWrite

Step 1.Fetch Instr.

Step 2.Access reg.

values.Select ALU to add

Step 3.ALU computes

address

Step 4.Store into memoryUpdate PC

0

DataMemory

data in

const

address

Comments:Need a MUX in front of ALURegWrite depends on opcodeconstant is 16 bits --> needs to be 32-bits

add


swstore word: sw $r1,const($r2) 43 r2 r1 const

InstructionMemory

RegisterFile ALU

$r2

$r1


r2

r1

RegWrite0

DataMemory

Const [ sign ext]

1

AddressMemWrite

WriteData

Mux

14


swstore word: sw $r1,const($r2) 43 r2 r1 const

RegisterFile ALU

$r2

$r1


r2

r1

RegWrite

DataMemory

const

Address

MemWrite

WriteData

01

Instr

ALUSrc

SgnExt

Controller

If opcode = 0 thenRegWrite = 1ALUSrc = 0MemWrite = 0ALUselect depends

on funct

Else if opcode = 43RegWrite =ALUSrc =MemWrite = ALUselect =


Verilog Break

Concatenation:Syntax: { }, separated by commasExample: x = {y0, y1, 0, 0, 1, y3};Sample Application: Composing a word made up of fields

Reptition: Syntax: {repetition_number{exp1, exp2,…, expn}}Example: x = {3{1,y0,y1,0}};

This is the same as x = {1,y0,y1,0, 1,y0,y1,0, 1,y0,y1,0};Sample Application: Sign or zero extension

Shifting:Syntax: x << constant or y >> constant. (Fills with zeros)Example: y = x << 2

Then y is a shifted version of x by 2 bit positions.Sample Application: Shifting, multiplying, or dividing.

15


Machine 5: lwload word: lw $r1,const($r2)

InstructionMemory

PC

DataMemory

data in

address

35 r2 r1 const

$r1$r2

+ALU

sign ext

data

RAM

Register File


Machine 5: lwload word: lw $r1,const($r2) 35 r2 r1 const

RegisterFile

ALU(+)

$r2

$r1


r2

r1

RegWrite

DataMemory

const

AddressMemWrite

WriteData

01

Instr

ALUSrc

SgnExt ReadData

Step 1.Fetch Instruction

Step 2.Get registersControllerprocesses

Step 3.Computeaddress

Step 4.Access memory

Step 5.Store in register

1

1

0

16


lwload word: lw $r1,const($r2) 35 r2 r1 const

RegisterFile ALU

$r2

$r1


r2

RegWrite = 1

DataMemory

const

Address

MemWrite = 0

WriteData

01

Instr

ALUSrc =1

SgnExt ReadData

01

(write data)

MemtoReg = 1

01

RegDst = 0

add

r1

r3


Machine 6: jj addr J-type instruction

PCInstructionMemory

2 Address (26 bits)

Shift left by 2 bits (add the last 2 zeros back)address is 28 bits

28 bits of address

+4

first 4 bits

17


jump

RegisterFile ALU

$r2

$r1


r2

RegWrite = 0

DataMemory

const

Address

MemWrite = 0

WriteData

01

Instr

ALUSrc =x

SgnExt ReadData

01

(write data)

MemtoReg = x

01

RegDst =x

x

r1

r3

InstrMemory

PC +[<< 2]

[31-28]01

jump = 14


Machine 7: beq

PCInstructionMemory

4 r1 r2 offset+4

beq $r1,$r2,offset I-type instruction

4 r1 r2 offset

$r1 $r2

-

<<2

Sign ext

+

1 0

targetbranching address

default

Register file

Check if zero

ALU

Zero = 1, if output = 00, if not 0

Zero

18


Single Cycle MIPS

Shift�left 2

PC


Read�address


Data�memory

Read�data

Write�data


Write�data

Read�data 1

Read�data 2

Read�register 1

Read�register 2




Add

ALU�result

Zero



RegWrite


ALUSrc


4

M�u�x


PC+4 [31– 28]

Sign�extend


1

M�u�x

1

0

M�u�x

0

1

M�u�x

0

1

ALU�control

Control

Add ALU�result

M�u�x

0

1 0

ALU

Shift�left 226 28

Address

1. Branch address computation

2. Check condition


Control: Truth Table

InstructionControl line add sub and or slt sw lw beqRegDstBranchMemReadMemtoRegALUSelMemWriteALUSrcRegWrite

19


Controller Implementation

Controller

RegDstBranchMemReadMemtoRegALUselMemWriteALUSrcRegWrite

Instruc[31-26]Instruc[15-0]

Controller

RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite

Instruc[31-26]

ALUControlInstruc[15-0]

ALUselInput Function000 AND001 OR010 add110 subtr111 set on less than

ALUOp Means Instr.00 add sw/lw01 sub beq10 R-type depends

on functfield

We canmake thissmaller

Two smallercontrollercircuits


Single Cycle MIPS

Shift�left 2

PC


Read�address


Data�memory

Read�data

Write�data


Write�data

Read�data 1

Read�data 2

Read�register 1

Read�register 2




Add

ALU�result

Zero



RegWrite


ALUSrc


4

M�u�x


PC+4 [31– 28]

Sign�extend


1

M�u�x

1

0

M�u�x

0

1

M�u�x

0

1

ALU�control

Control

Add ALU�result

M�u�x

0

1 0

ALU

Shift�left 226 28

Address

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EE361-SingleMIPS