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PHASE DIFFERENCE EFFECT ON POWER CONSUMPTION IN
WIRELESSLY POWERED CHARGE RECYCLING CIRCUITS
PRESENTED BY:SUSHIL PANDAGRADUATE RESEARCH
ASSISTANTELECTRICAL ENGINEERING
CURRENT INDUSTRY SITUATION OF INTEGRATED CIRCUITS
• 5.5 billion transistors on a commercially available IC
• Heat generated on the chip can be compared to that of a rocket nozzle
• Power dissipation has become a big issue and needs to be resolved soon
• Adiabatic circuits can be a possible solution to this situation
MOTIVATION FOR THE RESEARCH
• Battery present in various devices need to be charged in a timely manner• Medical implants rely on battery as their power source e.g. the
pacemaker, implantable cardioverter defibrillator• In order to recharge the battery a surgery needs to re-performed• If the battery can be recharged wirelessly, it would be a revolution.• Better so, if the circuits that the device is having can work directly
on the ambient energy!!!
ADIABATIC CIRCUITS: AN INTRODUCTION
• Also known as charge recycling circuits• Thermodynamic Definition of Adiabatic Circuits:
A process that does not involve the transfer of heat or matter into or out of system is called an adiabatic process
For circuits, charge is equivalent to heat/matter
• Many topologies present and many are still under study
• Basic working principle is very similar for all the topologies
• Work on AC signals unlike the presently used Static CMOS
UNDERSTANDING THE WORKING
Stack of papers: Energy SourceStudent writing: Circuits drawing power from the sourcePaper recycle: Charge getting transferred back to source
• The adiabatic circuit operation takes place in four intervals:• Evaluation: The circuit carries out the required
operation• Hold: The output is maintained for a certain
duration for the next stage to complete the evaluation
• Recover: The charge gets transferred back to the source
• Wait: To maintain symmetry in the power signal
UNDERSTANDING THE WORKING
• Analogy with real world situation• Imagine the student in the example replaced
by persons working in pipelined manner• One completes his/her work and passes it to
the next
CIRCUITS UNDER STUDY• Efficient Charge Recovery Logic (ECRL)
ECRL Inverter
4-bit Carry Ripple Adder
16-bit Carry Select Adder
• Complimentary Energy Path Adiabatic Logic (CEPAL)
CEPAL Inverter
4-bit Carry Ripple Adder
16-bit Carry Select Adder
Power comparison among Static CMOS, ECRL, CEPAL circuit:
Frequency
Static CMOS Power
CEPAL Power
ECRL Power
1 MHz4.28 1.37 0.95
5 MHz7.41 3.55 1.05
10 MHz11.33 5.93 1.30
20 MHz19.18 10.39 1.92
50 MHz42.73 19.63 4.27
100 MHz81.98 24.35 9.19
0 20 40 60 80 100 1200.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
80.00
90.00
Static vs ECRL vs CEPALStatic CMOS ECRL CEPAL
Operating frequency (in MHz)
Pow
er c
onsu
med
(in
mic
row
atts
)
PHASE DIFFERENCE BETWEEN THE POWER CLOCKS
• Lets assume the 4 persons working (in the example) are helping customers who are waiting in a line• Assume each person takes a certain amount of time to complete the
task, any deviation in the time would affect working of the next person• Similarly, for the circuits, various stages get power clocks that are a
certain phase apart from the previous stage• Any deviation would affect the power consumption by the following
stage• Core topic of the research was to determine the tolerable phase
difference which doesn’t hamper the power consumption and working
PHASE DIFFERENCE AND POWER CONSUMPTION IN ECRL
140 135 130 125 120 115 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40
PC1 0.46 0.45 0.45 0.44 0.44 0.44 0.44 0.43 0.43 0.43 0.43 0.43 0.44 0.44 0.46 0.48 0.53 0.62 0.77 1.00 1.36
PC2 2.12 1.46 1.02 0.73 0.55 0.44 0.39 0.36 0.35 0.34 0.34 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.34
PC3 0.47 0.30 0.28 0.28 0.28 0.28 0.27 0.27 0.27 0.27 0.27 0.27 0.28 0.28 0.28 0.28 0.28 0.28 0.29 0.29 0.29
PC4 0.26 0.26 0.26 0.26 0.25 0.25 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26
140 135 130 125 120 115 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40
PC1 0.44 0.43 0.43 0.43 0.43 0.43 0.43 0.43 0.43 0.43 0.43 0.42 0.43 0.43 0.44 0.43 0.44 0.44 0.44 0.44 0.44
PC2 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.34 0.34 0.35 0.36 0.39 0.45 0.56 0.75 1.06 1.54 2.29
PC3 1.90 1.28 0.87 0.61 0.45 0.36 0.31 0.29 0.28 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.28 0.30
PC4 0.38 0.28 0.26 0.26 0.26 0.26 0.26 0.25 0.25 0.25 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.27 0.27 0.27
Phase difference and power plotted different frequencies and following plots were obtained:
20 40 60 80 100 120 140 1600.000.501.001.502.002.50
PC1 sweptPC1 PC2 PC3 PC4
20 40 60 80 100 120 140 1600.000.501.001.502.002.50
PC2 sweptPC1 PC2 PC3 PC4
20 40 60 80 100 120 140 1600.001.002.003.00
PC3 sweptPC1 PC2 PC3 PC4
20 40 60 80 100 120 140 1600.000.501.001.502.00
PC4 sweptPC1 PC2 PC3 PC4
CONCLUSION
• Finally the tolerable/acceptable delay was found out that the person can avail without hampering the performance of the unit!!• It was found that beyond 30 degrees offset, the power
consumption for the circuit increases exponentially
A SPECIAL THANKS TO MY ADVISOR PROFESSOR EMRE SALMAN FOR HIS
GUIDANCE
