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IC Design Tutorial IV
DRC1. 要跑 Calibre 的第一步便是把 Layout 的”.db”給轉出來，選擇
”FileExportStream…”之後便會出現另一視窗
其中的”invdb”是自己要打的轉出檔案名稱，可自訂，或直接按此圖示
選擇轉出位置。
在此填入你所要轉出檔案的位置<”/grad/m92/kyoko/good/check/inv/drc/inv.db”>
1. 轉完之後在 Terminal 視窗下打”hpmenu” 或”sunmenu”選”b”(“f”)並打“calibre –gui”便可叫出 calibre 的界面選擇”DRC”便會叫出另一視窗
在此直接按”New Runset”即可
2. 之後選擇”Rules並在 Calibre-DRC Rules File 填入 Rules File 的位置
</disk/grad/m92/kyoko/good/TSMC035_2P4M/command_file/DRC/CM35S5
_4M.22b>或直接按此圖示去選擇位置”
並在”Calibre-DRC Run Directory 填入要跑的位置
</disk/grad/m92/kyoko/good/check/drc>”或按此圖示選擇位置
3. 填完按”Inputs”即可
5. 在”Files:”這裡填入剛才轉出”.db”檔的位置
</grad/m92/kyoko/good/check/inv/drc/inv.db >或按此圖示選擇位置，並在
”Primary Cell:”這裡填入主要的 Cell 名稱”inv”之後直接按 “Run DRC”便可
之後便會跑出如下視窗而其中這五個錯誤是可以忽略掉的
之後直接將此畫面關掉即可
6. 接下來因為我們所拷背的檔案中的
</disk/grad/m92/kyoko/good/TSMC035_2P4M/command_file/LVS/cali035pMM
5V_2P4M.lvs>並不是很正確，因此我們必須把檔案稍微修改一下<其中有8
個地方須修改>檔案如下:
"Calibre LVS Version V2.4a for TSMC 0.35um MIXED SINGAL POLYCIDE"
//
// @(#) T-035-MM-SP-002.lvs.rules Version T-035-MM-SP-002 V2.3a 04/29/2002
// @(#) TSMC 0.35um MIXED-SINGAL 2P4M POLYCIDE 3.3v/5v
// @(#) SPICE Doc. T-035-MM-SP-002 Rev. 2.4
//
// DISCLAIMER
//
// The information contained herein is provided by TSMC on an "AS IS" basis
// without any warranty, and TSMC has no obligation to support or otherwise
// maintain the information. TSMC disclaims any representation that the
// information does not infringe any intellectual property rights or proprietary
// rights of any third parties. There are no other warranties given by TSMC,
// whether express, implied or statutory, including, without limitation, implied
// warranties of merchantability and fitness for a particular purpose.
//
// STATEMENT OF USE
//
// This information contains confidential and proprietary information of TSMC.
// No part of this information may be reproduced, transmitted, transcribed,
// stored in a retrieval system, or translated into any human or computer
// language, in any form or by any means, electronic, mechanical, magnetic,
// optical, chemical, manual, or otherwise, without the prior written permission
// of TSMC. This information was prepared for informational purpose and is for
// use by TSMC's customers only. TSMC reserves the right to make changes in the
// information at any time and without notice.
//
////////////////////////////////////////////////////////////////////////////////
//
// USER NOTES :
//
// 1) mnpg49 mppg49 are obtained in a DRC run, not in an LVS run
//
// 2) Metal sheet resistance 0.085 except for top metal (0.05)
//
// 3) For Calibre "EDTEXT" file, use .INCLUDE strings.txt
// [text string] [x] [y] (layer name)
//
//
// CHANGE HISTORY
//
// Version Date Who Description
// ------- ---------- ---------- -------------------------------------------------
// 2.0a 04/12/2000 Jhtsai NEW CREATED.
// 2.1a 12/07/2000 T.C.Chiang modify Rs
// 2.3a 04/29/2002 Kevin Liu 1) modified Rs
// 2) revise P+/NW, N+/PW, NW/PW diode formation
// 2.4a 10/25/2002 Kevin Liu 1) Followed by the spice model version 2.4
//
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////
// SPECIFICATION STATEMENTS
//////////////////////////////////////////////
LVS HEAP DIRECTORY "/tmp"
LAYOUT PRIMARY "_cell_name"
LAYOUT PATH "_cell_name_.gds"
LAYOUT SYSTEM GDSII
//LAYOUT PATH "layout.net"
//LAYOUT SYSTEM SPICE
SOURCE PRIMARY "_cell_name_"
SOURCE PATH "_cell_name_.spi"
SOURCE SYSTEM SPICE
LVS POWER NAME "VDD" "AVDD" "VDD33" "VDD2" "VDDPST" "VDDLS" "VDD5V" "VDDG"
LVS POWER NAME "AVDDR" "AVDDG" "AVDDB" "AVDDBG" "TAVDD" "TAVDDPST"
LVS GROUND NAME "GND" "AGND" "VSS" "AVSS" "VSS2" "VSSPST" "VSSLS" "VSSG"
LVS GROUND NAME "AVSSR" "AVSSG" "AVSSB" "AVSSBG" "TAVSS" "TAVSSPST"
LVS REPORT "lvs.rep"
LVS ISOLATE SHORTS YES
DRC RESULTS DATABASE "calibre_drc.db" ASCII // ASCII or GDSII
DRC SUMMARY REPORT "calibre_drc.sum"
MASK RESULTS DATABASE NONE // "mask.db"
MASK SVDB DIRECTORY "svdb" QUERY
// DRC MAXIMUM VERTEX 199
PRECISION 1000
RESOLUTION 1
UNIT LENGTH U
TEXT DEPTH PRIMARY
VIRTUAL CONNECT COLON YES加入
VIRTUAL CONNECT NAME "?"加入
FLAG SKEW YES
FLAG OFFGRID YES
//////////////////////////////////////////////
// INPUT LAYER STATEMENTS
//////////////////////////////////////////////
DRC:1 = EXTENT
BULK = SIZE DRC:1 BY 1.0
LAYER NWELL 2
LAYER PIMP 7 //PP -- P+ S/D Implantation
LAYER NIMP 8 //NP -- N+ S/D Implantation
LAYER TDIFF 3 11 12 //OD -- Thin Oxide
LAYER OD2 4 //OD2-- Thick Oxide
LAYER N5V 6 //N5V-- 5V-NLDD
LAYER POLY1 13
LAYER POLY2 14
LAYER CONT 15
LAYER METAL1 16
LAYER VI1 17 //Via1 Hole
LAYER METAL2 18
LAYER PAD 19 //Passivation Window ( not use )
LAYER VI2 27 // Via2 Hole
LAYER METAL3 28
LAYER VI3 29
LAYER METAL4 31
LAYER BJTDUMY 49 //BJT dummy mask to form BJT
LAYER PSUB2 50 //apply for subtract2 ground
LAYER RWDUMMY 52 //DN_well resistor dummy mask
LAYER RODDMMY 75//dummy layer to remove OD
LAYER RPDUMMY 54 //dummy layer to form OD/POLY resistor
LAYER RMDUMMY 69 //dummy layer to form METAL resistor
LAYER DIODE 56 //dummy layer to form diode
LAYER PTDIODE 37 //dummy layer to form antenna diode
LAYER CDUMMY 68 //dummy layer to form poly1/m1/m2 C
TEXT LAYER 40 ATTACH 40 MT1
TEXT LAYER 41 ATTACH 41 MT2
TEXT LAYER 42 ATTACH 42 MT3
TEXT LAYER 43 ATTACH 43 MT4
PORT LAYER TEXT 40 加入
PORT LAYER TEXT 41 加入
PORT LAYER TEXT 42 加入
PORT LAYER TEXT 43 加入
// PORT LAYER TEXT 43
LAYOUT TOP LAYER METAL4 VI3 METAL3 VI2 METAL2 VI1 METAL1 PAD
LABEL ORDER MT4 MT3 MT2 MT1 C2POLY CPOLY NDIFF PDIFF PNSHORT PSUB NXWELL
VIRTUAL CONNECT COLON YES-殺掉
//////////////////////////////////////////////
// LAYER DERIVATIONS AND OPERATIONS
//////////////////////////////////////////////
// ;*********** POD*NOD-RODUMMY-->DIFF ***************************************
DIFF = TDIFF NOT RODDMMY
// ;*********** Define DIFF/POLY1/POLY2/Metal Resistor ***********************
DRDUM = RPDUMMY INTERACT DIFF //DIFF RESISTOR DUMMY
RP1 = RPDUMMY NOT INTERACT DIFF
P1RDUM = RP1 INTERACT POLY1 //POLY1 RESISTOR DUMMY
RP2 = RP1 NOT INTERACT POLY1
P2RDUM = RP2 INTERACT POLY2 //POLY2 RESISTOR DUMMY
// ;To form diffusion resistor
RESD = DIFF AND DRDUM //diff resistor layer
RESDN = RESD AND NIMP //n+od resistor
RESDP = RESD AND PIMP //p+od resistor
MDIFF = DIFF NOT RESD //diff region
// ;To form poly1 resistor
RESP1 = POLY1 AND P1RDUM //poly1 resistor layer
RESPP = RESP1 AND PIMP //p+poly1 resistor
RESPN = RESP1 NOT RESPP //poly1 resistor
CPOLY = POLY1 NOT RESP1
// ;To form poly2 resistor //poly2 resistor layer
RESP2 = POLY2 AND P2RDUM
C2POLY = POLY2 NOT RESP2
// ;To form metal1 resistor
MT1RES = METAL1 AND RMDUMMY //define metal1 resistor
MT1 = METAL1 NOT MT1RES
MT2RES = METAL2 AND RMDUMMY //define metal2 resistor
MT2 = METAL2 NOT MT2RES
MT3RES = METAL3 AND RMDUMMY //define metal3 resistor
MT3 = METAL3 NOT MT3RES
MT4RES = METAL4 AND RMDUMMY //define metal4 resistor
MT4 = METAL4 NOT MT4RES
//
// ;********** Define POLY1/POLY2 Capacitor **********************************
CAPPL = POLY1 AND POLY2 //POLY1*POLY2 --> CAPPL
// ;********** Define N_Well Resistor ****************************************
RWELL = RWDUMMY AND NWELL
NXWELL = NWELL NOT RWELL
// ;********** Apart P_SUB by PSUB2 and NWELL ********************************
PPSUB = BULK NOT NWELL
PSUB2S = SIZE PSUB2 BY 0.03
PSUB1 = PPSUB NOT PSUB2S
PSUB2A = PPSUB AND PSUB2
PSUB = PSUB1 OR PSUB2A //PSUB=[(BULK-NWELL)-SIZE(PSUB2)]+
// //[(BULK-NWELL)*PSUB2]
// ;********** Define MOS Gate-Type *******************************************
ODN = OD2 AND N5V
ODP = OD2 NOT N5V
ODALL= OD2 OR N5V
GATE = CPOLY AND MDIFF
TPGATE = GATE AND PIMP
TNGATE = GATE AND NIMP
PGATE = TPGATE NOT ODALL
NGATE = TNGATE NOT ODALL
BPGATE = TPGATE AND ODP
BNGATE = TNGATE AND ODN
// ;************ Define P/N Diffusion Region **********************************
PTHIN = MDIFF AND PIMP
NTHIN = MDIFF AND NIMP
// ;************ Define P/N Source/Drain Region *******************************
PDIFF = PTHIN NOT GATE
NDIFF = NTHIN NOT GATE
BUPDIF = PDIFF INTERACT NDIFF
BUNDIF = NDIFF INTERACT PDIFF
PNSHORT = BUNDIF OR BUPDIF
// ;************ Define Substrate Contacts ************************************
PPLUG = PDIFF AND PSUB //define p_sub contact
NPLUG = NDIFF AND NXWELL //define N_well contact
// ;************ Define BJT ***************************************************
TTDIFF = BJTDUMY AND PDIFF //define BJT p+ region
DRC:2 = HOLES TTDIFF
PNPTR = DRC:2 NOT PDIFF
EMIT = TTDIFF INSIDE NXWELL //define BJT emitter
COLL = TTDIFF NOT INSIDE NXWELL //define pnp bipolar device
// ;************ Define 2-poly contacts ***************************************
PL2CO = POLY2 AND CONT
PL1CO = CONT NOT PL2CO
DCONT = PL1CO NOT POLY1
// ;*********** Define connect ************************************************
CONNECT MT1 C2POLY BY PL2CO
CONNECT MT1 CPOLY BY PL1CO
CONNECT MT1 NDIFF PDIFF BY DCONT
CONNECT MT2 MT1 BY VI1
CONNECT MT3 MT2 BY VI2
CONNECT MT4 MT3 BY VI3
SCONNECT PDIFF PSUB BY PPLUG
SCONNECT NDIFF NXWELL BY NPLUG
SCONNECT PDIFF PNSHORT BY BUPDIF
SCONNECT NDIFF PNSHORT BY BUNDIF
COLL:1 = STAMP COLL BY PDIFF
EMIT:1 = STAMP EMIT BY PDIFF
// ;*************** Define MOS S/D Region *****************************
PPDIFF = PDIFF NOT ODALL
PNDIFF = NDIFF NOT ODALL
BPDIFF = PDIFF AND ODP
BNDIFF = NDIFF AND ODN
// ;*************** Define Diode P/N Region *****************************
// define device -- diode DP
pdio1 = PDIFF AND DIODE
pdio = pdio1 AND NXWELL
//
// define device -- diode DN
ndio1 = NDIFF AND DIODE
ndio = ndio1 AND PSUB
//
// define device -- diode DW
DIONW = DIODE OUTSIDE PDIFF
nwdio = NXWELL AND DIONW
//PDIO = PDIFF AND DIODE
//NDIO = NDIFF AND DIODE
//PTNDIO = NDIFF AND PTDIODE
// ;*************** Define Device MOS,DIO AND BJT ************************
DEVICE MN(N) NGATE CPOLY PNDIFF PNDIFF PSUB [0] //define Nmos in p_sub
TRACE PROPERTY MN(N) L L 2
TRACE PROPERTY MN(N) W W 2
DEVICE MP(P) PGATE CPOLY PPDIFF PPDIFF NXWELL [0] //define Pmos in n_well
TRACE PROPERTY MP(P) L L 2
TRACE PROPERTY MP(P) W W 2
DEVICE MN(ND) BNGATE CPOLY BNDIFF BNDIFF PSUB [0] //define HV-Nmos in p_sub
TRACE PROPERTY MN(ND) L L 2
TRACE PROPERTY MN(ND) W W 2
DEVICE MP(PD) BPGATE CPOLY BPDIFF BPDIFF NXWELL [0] //define HV-Pmos in n_well
TRACE PROPERTY MP(PD) L L 2
TRACE PROPERTY MP(PD) W W 2
DEVICE Q(PV) PNPTR COLL:1 NDIFF EMIT:1 //define pnp BJT
//DEVICE D(DP) DIODE PDIO NDIO //define diode
//DEVICE D(DN) PTNDIO PSUB NDIFF //define antenna protection diode
DEVICE D(DP) pdio PDIFF NXWELL // define P+/NW diode
TRACE PROPERTY D(DP) A A 10
DEVICE D(DN) ndio NDIFF PSUB // define N+/PW diode
TRACE PROPERTY D(DN) A A 10
DEVICE D(DW) nwdio PSUB NXWELL // define NW/PW diode
TRACE PROPERTY D(DW) A A 10
// ;*************** Define Resistor ******************************************
DEVICE R(M1) MT1RES MT1 MT1 [0.083] //define metal resistor
TRACE PROPERTY R(M1) R R 10
DEVICE R(M2) MT2RES MT2 MT2 [0.080]
TRACE PROPERTY R(M2) R R 10
DEVICE R(M3) MT3RES MT3 MT3 [0.080]
TRACE PROPERTY R(M3) R R 10
DEVICE R(M4) MT4RES MT4 MT4 [0.051]
TRACE PROPERTY R(M4) R R 10
DEVICE R(WR) RWELL NXWELL NXWELL [1050] //define n_well resistor
TRACE PROPERTY R(WR) R R 10
DEVICE R(P1) RESPN CPOLY CPOLY [8.0] //define poly1 resistor
TRACE PROPERTY R(P1) R R 10
DEVICE R(PR) RESPP CPOLY CPOLY [8.0] //define p+poly1 resistor
TRACE PROPERTY R(PR) R R 10
DEVICE R(P2) RESP2 C2POLY C2POLY [50.0] //define ploy2 resistor
TRACE PROPERTY R(P2) R R 10
DEVICE R(PD) RESDP PDIFF PDIFF [150] //define p+od resistor
TRACE PROPERTY R(PD) R R 10
DEVICE R(ND) RESDN NDIFF NDIFF [80] //define n+od resistor
TRACE PROPERTY R(ND) R R 10
// ;********** Define Capacitor ********************************************
DEVICE C(PC) CAPPL CPOLY C2POLY [8.9e-4 7.3e-6] //define poly cap.
TRACE PROPERTY C(PC) C C 10
MCAP1 = CDUMMY AND METAL1
MCAP2 = MCAP1 AND METAL2
MCAP3 = MCAP2 AND POLY1
DEVICE C(MC) MCAP3 MT1 MT2 [9.0e-5 5.34e-5]
TRACE PROPERTY C(MC) C C 10
// ;**************************************************************************
// ;********** ERC CHECK *****************************************************
// ;**************************************************************************
// ;1.check sbustrate soft-connect short
// ;2.check same label at different net and different label at same net
// ;3.check mos pin connect to power, ground
// ;4.check path
// ;5.check p-diff short n-diff with different voltage
// ;********** Substract soft-connect short check ****************************
// ;Reports regions on a psub layer that connect to more than one node.
// ;Reports regions on a nxwell layer that connect to more than one node.
// ;Reports regions on a p-diff&n-diff short that connect to more than one
// ;If the error happen, check <svdb.dir>/topcell.softchk, By default
// svdb.dir is current directory
LVS SOFTCHK PSUB CONTACT
LVS SOFTCHK NXWELL CONTACT
LVS SOFTCHK PNSHORT LOWER
// ;********* Check Same Label and Mult-label ********************************
// Checked in Calibre LVS by default
// ;********** Path check ****************************************************
// ;Nodes with a path to ground but not to power
// ;Nodes with a paht to power but not to ground
// ;Nodes without a path neithor power nor ground
// ;Nodes without a path to power, ground, or pads, where pads are labeled
// If the error happen, check <svdb.dir>/topcell.pathchk.erc, BY default
// svdb.dir is current directory
ERC PATHCHK GROUND && !POWER
ERC PATHCHK POWER && !GROUND
ERC PATHCHK !POWER && !GROUND
ERC PATHCHK !LABELED
// ;********** Check mos connect to power or ground **************************
// Following checks are obtained in a DRC run, not on LVS run. Please run
// Calibre -drc <this file>
econ1 = NET ndiff "VDD?" "AVDD?" "TAVDD?"
mnp = ngate TOUCH econ1 // nmos S/D connected Power
econ2 = NET ndiff "?GND" "VSS?" "AVSS?" "TAVSS?"
mng = ngate TOUCH econ2 // nmos S/D connected Ground
econ3 = NET pdiff "?GND" "VSS?" "AVSS?" "TAVSS?"
mpg = pgate TOUCH econ3 // pmos S/D connected Ground
econ4 = NET pdiff "VDD?" "AVDD?" "TAVDD?"
mpp = pgate TOUCH econ4 // pmos S/D connected Power
mnpg49 { mnp AND mng } // nmos S/D connected P&G
mppg49 { mpg AND mpp } // pmos S/D connected P&G
ptap = pdiff AND psub
xwell = NWELL OUTSIDE RWDUMMY
ntapx = ndiff AND xwell
ntap = ntapx NOT BJTDUMY
ppvdd49 { NET ptap "VDD?" "AVDD?" "TAVDD?" }
npvss49 { NET ntap "?GND" "VSS?" "AVSS?" "TAVSS?" }
// ;**************************************************************************
// ;* LVS Check Option ******************************************************
// ;**************************************************************************
LVS SPICE PREFER PINS YES
LVS ABORT ON SUPPLY ERROR NO
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS IGNORE PORTS YES改NO
LVS RECOGNIZE GATES ALL
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE SPLIT GATES YES
LVS FILTER UNUSED OPTION B D E O
LVS FILTER UNUSED OPTION AB RC RE RG
改完後按”save”即可
