IO_Pads

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I/O PADSIn, Out , InOut , Gnd , Vdd,

Source follower

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Bidirectional Pad -

Digital Component.

Operates as Pad_in or Pad_out:

EO high => pad out.

EO low => pad in.

pad

dataInUnBuff

dataOut

EO

DataIn

DataInBPadBidirHE_SCMOS

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Pad Layout

DataInOE DataOutDataInUnBufDataInBuf

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Pad In DC Analysis

DataInB, after one inverter, has less gain than dataIn

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

vpad (V)

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Voltage(

V)

v(dataInB)v(dataIn)v(pad)

simIn

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Max frequency 100Mhz

Dx = 4.11nsec (>80%*5=4nsec)

Cursers mark position where output exceed 80% of max input value

VinBar

Vin

Vpad

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Pad out Dc Analysis

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

vdataout (V)

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Voltage(V)

v(pad)

v(dataout)

simOut

DataOut

Pad

DataInB

DataIn

DataInUnBuf

OE

OE

OEB

OEB R =

1 0 0

T0

L=2u

W=22uT0

L=2u

W=22uT0

L=2u

W=22uT0

L=2u

W=22u

T0

L=2u

W=22u

T0

L=2u

W=22u

BONDING

PAD

T0

L=2u

W=22uT0

L=2u

W=22uT0

L=2u

W=22uT0

L=2u

W=22u

T0

L=2u

W=22u

T0

L=2u

W=22u

Response similar to dataIn.

Explanation: It has twolevels of amplifying, as the

dataIn node.

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

vpad (V)

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Voltage(V)

v(dataInB)v(dataIn)v(pad)

simIn

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Max frequency 30Mhz

with 10pF capacitor as load

Vpad

DataOut

Dx = 14.06nsec (> 80%*17=13.6nsec)

Cursors mark position where output exceed 80% of max input value

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Sfwith no ideal current source

Function: Pad follows Signal, with DC offset.

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SFLayout

Signal

Vdd

Vss

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SF behavior (with the pmos as

current source)Current source values-190 to -150 uA

0

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Lets have a closer look

VpadVsignal = 0.85 constant when 0 < Vsignal

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Slew Rate of the SFVsignal

Vpad

Vpad-Vsignal

Vsignal = ramp from 0 to 5v in 1usec

The SF still follow the step in the range of 0

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Pad I/O With ESD

Two diodes are placed to protect the chip, and are normally at reversecharge.

When signal exceeds 5+Vb volts, then D2 is forward biased and

discharges the excess voltage.

When signal is belowVb, then a similar discharging process occurs

through D1.

D2

D1

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PadIOEsd Layout

Diode 1D1 inschematic

Diode 2 D2 inscehematicsignal

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Modeling the Pad

The modeling was done

by attaching a capacitor,

and a resistor, to the pad.

They reperesent thecapacitance and

resistance of three main

models: Human,

machine, and package.

SIGNALSIGNAL

vinit

Gnd

V=5.0

R=1.

5K

BONDING

PAD

Dpdiff

Dndiff

C=100pF

To run simulation, an initial voltage was initialized

on the model.

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Human model.

R=1.5k, C=100pF,

Initial Voltage = 2kV

0 50 100 150 200 250 300 350 400 450 500

Time (ns)

0.5

1.0

1.5

2.0

Voltage(kV)

v(vinit)

s i m P a d W i t h E S D _ h u m a n _ m o d e l n e w

0 50 100 150 200 250 300 350 400 450 500

Time (ns)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Current(A)

i1(R4)


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Machine Model.

R=25, C=200pF,

Initial Voltage = 200V

0 5 10 15 20 25 30 35 40 45 50

Time (ns)

0

50

100

150

200

Voltage(V)

v(vinit)


0 5 10 15 20 25 30 35 40 45 50

Time (ns)

0

1

2

3

4

5

6

7

8

Current(A)

i1(R4)


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Package Model

R=1, C=1.5pF,

Initial Voltage = 2kV

0 10 20 30 40 50 60 70 80 90 100

Time (ps)

0.0

0.5

1.0

1.5

2.0

Voltage(kV)

v(vinit)


0 10 20 30 40 50 60 70 80 90 100

Time (ps)

0.0

0.5

1.0

1.5

2.0

Current(kA)

i1(R4)


Documents

IO_Pads