Low Power Design on SoC

Member : 張民杰 P90921010

郭光爵 P91921004

黃興洋 R91922047

Speaker : 郭光爵

Outline

Why Low Power ? Design Issues on Power Consumption Key Criteria for Power Reduction General Approaches Conclusion

Outline

Why Low Power ? Design Issues on Power Consumption Key Criteria for Power Reduction General Approaches Conclusion

Motivation of Low Power

Energy-efficient computing is required by Mobile electronic systems Large-scale electronic systems

Requirement of energy efficiency affects all aspects of system design Packaging costs Cooling costs Power supply rail design Noise immunity and system reliability

Technology Directions

year 1999 2002 2005 2008 2011 2014

Feature size (nm)

180 130 100 70 50 35

M trans/cm2 7 26 47 115 284 701Chip size (mm2) 170 214 235 269 308 354Signal pins 768 1024 1204 1280 1408 1472Clock rate 600 800 1100 1400 1800 2200Wiring level 7 8 9 9 10 10voltage 1.8 1.5 1.2 0.9 0.6 0.6Power(W) 90 130 160 170 174 183

Chip Power Densities

Outline

Why Low Power ? Design Issues on Power Consumption Key Criteria for Power Reduction General Approaches Conclusion

Basic Concepts (1/2)

P = CLVDD2f 01 + tsc VDD Ipeak f 0 1 + VDD Ipeak

Dynamic term (~90%) CLVDD2f 01

Short-circuit term (~8%) tsc VDD Ipeakf 0 1

Leakage term (~2%) VDD Ipeak

Dynamic Power Power dissipation due to capacitance charging at

transitions from 0 1 and 1 0

Basic Concepts (2/2)

Short-Circuit Power Power consumption due to brief short-circuit

current during transitions

Static Power Steady, per-cycle energy cost, e.g. Leakage Power More important issue in deep submicron

Mostly focus on dynamic, but recently work on others

Hierarchical Design (1/2)

Hierarchical Design (2/2)

Outline

Why Low Power ? Design Issues on Power Consumption Key Criteria for Power Reduction General Approaches Conclusion

Voltage Supply (Vdd)

Biggest impact : 50% reduction in Vdd, 75% reduction in power

Can not be reduced indefinitely (can’t be too close to Vt – lower Vt means higher leakage power – and lower Vdd increases latency)

Power-driven voltage scaling Pipelining, Parallelization, Loop unrolling Multiple voltages

Slow down non-critical path with lower voltage supply Two or more power grids

Clock Frequency (fclk)

Has significant impact only in conjunction with Vdd scaling

Lowering only f does not decrease energy But it may increase battery life Reduce average power Energy throughput becomes worse

Multi-frequency clocks

Load Capacitance (CL)

Roughly proportional to the chip area Can be reduced by re-synthesis or re-design for

low power Reduce wiring capacitance

Reduce local loads Reduce global interconnect

Global interconnect can be reduce by improving spatial locality : trade off communication for computation

Switching Activity (f01)

Very data depedent A big portion due to glitches (real-delay) –

reducing glitches Can be reduced by power sensitive data

encoding, re-synthesis (e.g. balanced designs) Improve correlation between consecutive input

to functional macros Synergistic high-level-synthesis approaches

lead best results

Outline

Why Low Power ? Design Issues on Power Consumption Key Criteria for Power Reduction General Approaches Conclusion

Power Estimation (1/3)

Gate level – challenges Need node-by-node accuracy Vdd, fclk, CL are known

Actually, layout will determine the interconnect capacitance

Need to estimate switching activity accurately

Spatial and temporal dependencies – circuit and input included

Power Estimation (2/3)

RT/Microarchitectural level – challenges Details of IP core implementation is largely

unknown Have to abstract switching activity and

capacitance values Less accurate, but more efficient

Efficient design space exploration

Power Estimation (3/3)

Software and system level – challenges Very few implementation details available Need to rely on accurate lower level

estimation tools Complexity can be prohibitive for highly

accurate estimates

SimplePower SystemFramework

SimplePower Compilation Framework

Other Related Tools

Intel Tempest Princeton Wattch IBM PowerTimer

Power Optimization (1/4)

Gate level Mostly targets CL and switching activity

reduction Reduce power via

Logic synthesis Precomputation / guarded evaluation Clock gating

Power Optimization (2/4)

RT/Behavioral/Microarchitecture level Mostly targets CL, switching activity, as well

as joint Vdd/fclk reduction Need to rely on high-level (maybe not so

accurate) estimates Low power register sharing Low power module assignment Multiple supply voltage assignment Bus encoding

Power Optimization (3/4)

Software level Per-instruction cost, plus inter-instruction

effects Ep = Σ (Bi x Ni) + Σ(Oi,j x Ni,j) + Σ Ek Modified list scheduling algorithm for low power

instruction scheduling Operation packing Operand swapping

Power Optimization (4/4)

System level Platform-based design

Workload specific mapping Application and platform modeling and mapping

Dynamic power management Operating System – driven Microarchitecture and Software supported ACPI, DPM “Energy Aware Computing”

Yung-Hsiang Lu, Luca Benini, Member, IEEE andGiovanni De Micheli, Fellow, IEEE Power-Aware Operating Systems for Interactive System,IEEE Trans. on VLSI

Voltage Islands

Two basic ideas of the voltage island Multiple Voltages for different sub-cirsuits Power Management

References D. E. Lackey, P. S. Zuchowski, T. R. Bednar, “Managing Power

and Performance for System-on-Chip Design using Voltage Islands,” ICCAD 2002, page: 195-202

K. Roy, S. C. Prasad, Low-Power CMOS VLSI Circuit Design, Wiley-Interscience publication, 2000

Outline

Why Low Power ? Design Issues on Power Consumption Key Criteria for Power Reduction General Approaches Conclusion

Conclusion

For a complete low power solution, hardware/software synergy is essential

Need for novel microarchitectural paradigms that address the problem of joint power-performance optimization

Low power design is still a HOT problem

Reference K. Roy, S. C. Prasad, “Low-Power CMOS VLSI Circuit Design,”

Wiley-Interscience publication, 2000 Yung-Hsiang Lu, Luca Benini, Member, IEEE and Giovanni De Micheli,

Fellow, IEEE “Power-Aware Operating Systems for Interactive System,” IEEE Trans. on VLSI

W. Ye, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, “The Design and Use of SimplePower : A Cycle-Accurate Energy Estimation Tool,” Microsystems Design Lab, The Pennsylvania State University

D. E. Lackey, P. S. Zuchowski, T. R. Bednar, “Managing Power and Performance for System-on-Chip Design using Voltage Islands,” ICCAD 2002, page: 195-202

“Platune: A Tuning Framework for System-on-a-Chip Platforms,” IEEE Trans. on CADICS, Vol. 21,No. 11,November 2002

Reference (Cont.) “Energy-Driven Integrated Hardware-Software Optimizations

Using SimplePower,” Microsystems Design Lab, The Pennsylvania State University

“Energy-Oriented Compiler Optimizations For Partitioned Memory Architectures,” Power & Energy Management Light Seminar, March 29, 2001

Hang-Sheng Wang, Li-Shiuan Peh and Sharad Malik, “How HOT Are Interconnection NetWorks - A Power Model for Routers,” Princeton University

HoJun Shim, “Energy Estimation Tools for Low Power,” System Computer Systems Lab., Seoul National University

Power-Aware Operating Systems for Interactive Systems

Yung-Hsiang Lu, Luca Benini, Member, IEEEGiovanni De Micheli, Fellow, IEEE

Speaker : 黃興洋

Outline Introduction Background Knowlege Process-Based Power Management On Line Scheduling Experiments and Results Conclusion

Introduction Power is a precious resource and should be

properly managed. Low power consumption prolongs operatio

n hours of battery-powered system, while high power raises temperature and deteriorates reliability.

A low power OS kernel can help to estimate the utilization of a device and decide its power state.

Introduction(cont) Power reduction techniques : Static a

nd Dynamic. Here in the interactive system, we need the second.

This paper present a new approach for using OS to reduce the power consumption in I/O devices.

Background Knowlege Scheduling : When multiple processes req

uire the same resource, such as CPU or hard disk, the OS determine their access orders is called scheduling.

Jobs : defined as a unit to finish a specific task and can be scheduled to start at specific time. For example, text editor formatting, spell checking, and saving are distinct jobs.

Background Knowlege Precedence and timing constraints Scheduling jobs for power manageme

nt

SchedulingSuch as round-robin, priority, and FIFO.

Job Precedence

Scheduling for Power Management

Process Based Power Management Request generation models Device utilization Shut down condition

Request Generation ModelExisting DPM policies do not distinguish req

uest sources. They assume that the arrival of requests is sufficient for predicting the length of future idle period.

We adopt a new model for request generation

Separates request sources by processes Detects the termination of a process Considers how often a process executes

Device UtilizationTwo factors of device utilization : How often the process generate reque

sts ? How often the process runs ?

Device Utilization(cont)We use discounted average to estimate tbr a

nd utilization.

1)1( nn tbratbratbr

tbr: time between request

a: a constant between zero and one

uij: utilization of device i by process j

nij

tbru

1

Device Utilization(cont))

,(

ibe

ij

ijt

lef

ijijij fuw fij: to estimate the change of process from IO burst to CPU burst

lij: the time since the last request

wij: new estimation with regard to process condition

Shut Down ConditionThe shut down condition is :

If k is one, a device is shut down when the utilization is smaller than 1/tbe, namely the time between request from all processes is longer than tbe.

When k is smaller than one, the power manager is conservative, this may lose opportunities to save power.

If k is larger than one, the power manager is aggressive, because it takes chances to save power by shutting down the device even when the utilization is still high.

K suggested to be equal to or slightly more than one.

ibei t

ku,

On Line Scheduling Requests created by timer Predictive wake up Flexible timers Scheduling jobs for power reduction

Request Created by Timer Some requests are created by timer :In Unix, the job is created in four steps :1) Calling setitimer to create a timer2) Register a callback function for the S

IGALARM signal3) OS issues SIGALARM signal when the

timer expires4) Execute a callback function

Predictive Wake Up

Predictive Wake Up(cont)

Flexible Timers

Flexible Timers(cont)

Scheduling Jobs For Power Reduction

Experiment and ResultsPlatform : Linux Red Hat on Sony VAIO notebook OS control the IO device through PCMIA int

erfaces with suspend and consume commands to control devices. These commands can shut down and wake up devices

Notebook is an interactive system with fast response and wide variety of apps

Conclusion Point out the importance to distinguis

h individual processes for power management

Propose a power-aware scheduling for IO request (a low power scheduling algorithm)

They have an implementation on Linux and obtain significant power saving.