Microsoft PowerPoint - Delta_sigma_PLL[1]1
• PLL fundamental
• Fully differential PLL architecture
• A 3rd order Σ modulated fractional-N frequency synthesizer and its building blocks
Fuding Ge: PLL and Frequency Synthesizer 2001
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Fuding Ge: PLL and Frequency Synthesizer 2001
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V(t)=V0[cosω0t + φcos(ω0+ωm)t/2 − φcos(ω0-ωm)t/2]
– The last two terms are spurious tone. One spur is ωm
above ω0 and one is ωm below ω0.
Fuding Ge: PLL and Frequency Synthesizer 2001
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PLL Fundamental
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PLL Fundamental
Fuding Ge: PLL and Frequency Synthesizer 2001
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)]CC(sR)[(1Cs(C
Open Loop Gain:
• Three Poles: two at zero (so type II) frequency, one at
τp= R(C0↔C1)≅ RC1
• Crossover frequency: 10
Fuding Ge: PLL and Frequency Synthesizer 2001
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ω
ω
ωz
ωp
GAIN
PHASE
-90
-180
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• Fixed bandwidth to operating frequency ratio
• Charge pump current, VCO gain and loop filter resistance are
not constant, so fast locking time
• No external biasing
• Low sensitivity to power supply and substrate noise
• Low static phase error Reference: J.G. Maneatis: JSSC, Vol 31, No.11, , pp 1723-1732, 1996
Fuding Ge: PLL and Frequency Synthesizer 2001
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C1
C2
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Td=RefCef=(1/gm)Cef=Cef/[k(Vctrl-Vt)
This circuit shows low phase noise, see Liang Dai et al: 2000 ISCAS: Comparison and Analysis of Phase Noise in Ring Oscillators
I=2ID
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Self Biased PLL
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Self Biased PLL
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Self Biased PLL
Almost symmetric at the same point, but with different resistance !
Fuding Ge: PLL and Frequency Synthesizer 2001
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Work AsIch=x(2ID)
Self Biased PLL
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•Bias current changes with frequency
•Damping factor is constant if Ich is proportional to VCO bias current (2ID) and loop
filter resistor is inversely proportional to the square root of ID , which can be formed
by the 1/gm of the diode connected symmetric load. Then we have
NC
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Self Biased PLL
Conceptual bias diagram
• Dynamically adjusts NMOS current source to achieve high static
power supply noise rejection
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Self Biased PLL
Pbias=Vctrl
Size is the size of VCO load divided by y, forms R in the loop filter
2ID/y
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2ID
B
Tctrl
1 F
−•== CB=2nCef is the total buffer output capacitance for all stages, k is the device transconductance
Kvco=|dF/(dVctrl)| = k/CB
Self Biased PLL
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51 MHz
979 MHz
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122
N
2212
2
2
1
12
1
242
1
2
ππ
The only process dependence is a ratio of capacitance that can be matched quite well through proper layout.
Self Biased PLL
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• The effects of current mismatch and charge sharing
reduced
• Differential output less sensitive to leakage current
• Better immunity to power supply, ground and
substrate noise
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Switched Capacitor Negative Resistance
PHase Select + /2/3 Cell MMD (8)
3rd Order Digital Σ Modulator
PRSG + Digital HPF (Dither)
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TSPC DFF
Basic Building Block: DFF, can be used in PFD and prescaler
Fuding Ge: PLL and Frequency Synthesizer 2001
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Basic Building Block:PFD
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Reference spur:
fref=200Khz, fBW=20KHz, fout=2GHz, fpl=80KHz, Icp=1mA, Ileak=1nA, Pr=-55 dBc
Solution: Narrow bandwidth, Increase current (?)
•Mismatches in Charge Pump:
•Solution: Careful Circuit Design
Fuding Ge: PLL and Frequency Synthesizer 2001
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(a) Simple Charge pump
Fuding Ge: PLL and Frequency Synthesizer 2001
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Basic Building Block: Charge Pump
Fuding Ge: PLL and Frequency Synthesizer 2001
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Fuding Ge: PLL and Frequency Synthesizer 2001
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Basic Building Block: Charge Pump
Fuding Ge: PLL and Frequency Synthesizer 2001
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Fuding Ge: PLL and Frequency Synthesizer 2001
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(a)
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• Design equation: gM3=αRp(2πfoscCvar) 2
• gm=2I/(VGs-Vt)=√(2βI)
⇒ small tuning range
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Fuding Ge: PLL and Frequency Synthesizer 2001
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Basic Building Block: VCO
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Switched Capacitor VCO
To reduce noise from DAC and voltage adder, voltage summation placed before LPF
• Low power supply
Fuding Ge: PLL and Frequency Synthesizer 2001
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Lo Chi Wa, HKUST, 2000
Basic Building Block: Switched Capacitor VCO
Fuding Ge: PLL and Frequency Synthesizer 2001
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Switched capacitor tuning LC Oscillator
Basic idea: using switched capacitors to do coarse tuning, then use varactor do fine tuning
LC
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Basic Building Block: D Latch
The correct function of the latch depends on the proper size of the transistors
Fuding Ge: PLL and Frequency Synthesizer 2001
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Building Block: Frequency Divider
Note the 90 degree phase difference between signal x, y, xb, yb. This can used with the phase selection design
LatchLatch
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N out mcmcmcf 2222 3
3 2
2 1
1 ++++= L
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Output Spectrum for Frequency Switching controlled by 1st , 2nd , 3rd and 5th Delta-Sigma mod
Σ modulator
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Output Spectrum for randomized 1st and 2nd Σ modulator input with randomization factor of 0.5 and 1.0
Hiok-Hion Ng, ASU Master Thesis, Dec 1999 1st Order,
RF=0.5
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Circuit Complexity ↑ • Research shows: 3rd order is good enough
– Require: 23=8 modulus (3 bits) for MMD
– Require 4th order loop filter
• Research shows 24-bit accumulator provided resulting in enough accuracy
Mucahit Kozak et al: IMTC 2000
Σ modulator
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• MASH (MultistAge noise SHaping) • Cascade of low order Σ Modulator
• Stable
• Can easily be implemented using pipeline structure
• Multibit output requires multi modulus divider – Example: MASH-3: 3 bits output, ⇒ 8 MMD
Σ modulator
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Dither +
N(k)
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Σ Modulator
• Accumulator can be implemented using pipeline structure, no input and output alignment registers are needed.
Reference: Mucahit Kozak et al: A pipeline all-digital delta-sigma modulator for fractional-N frequency synthesis, IMTC 2000, pp1153-1157
• Dither can be implemented by a pseudo random sequence generator (PRSG) followed by a digital high pass filter. High pass filter just some combinations (adder) of (1-z-1) operators
• Quantization noise cancellation network can be implemented with (1-z-1) operators and adders, no alignment registers required.
Σ modulator
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Basic Building Block: Full-Adder, can be used in Delta-Sigma Modulator
A.M. Shams et al: IEEE Trans Cir & System-II: Vol47, 2000, PP478-481
Fuding Ge: PLL and Frequency Synthesizer 2001
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XOR Gate
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Digital Filter
X z
z y
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z-1 z-1
z-1 1-z-1
1-z-1 1-z-1
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• 2nd Modulator, 22 bit resulution, 2 bits output
• -103 dBc/Hz (VCO=950MHz, Vref=20MHz)
• 4mmx4mm 24-pin BCC package, BiCMOS
• Power: 7.5 mA