RTL CodingGuide

8/7/2019 RTL CodingGuide

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25-Aug-05 EM 7021 System On Chip

RTL Coding GuidelinesRTL Coding Guidelines

Trio Adiono Trio Adiono


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25-Aug-05 EM 7021 System On Chip 2

ObjectiveObjective ReadableReadable ModifiableModifiable ReusableReusable Simple & regular structureSimple & regular structure

Easy to design, code, verify, synthesizeEasy to design, code, verify, synthesize Meet performance and functional goalMeet performance and functional goal


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Coding GuidelinesCoding Guidelines Use simple constructs, basic types (for VHDL), andUse simple constructs, basic types (for VHDL), and

simple clocking schemes.simple clocking schemes. Use a consistent coding style, consistent naming Use a consistent coding style, consistent naming conventions, and a consistent structure for processesconventions, and a consistent structure for processesand states machines.and states machines.

Use a regular partitioning scheme, with all moduleUse a regular partitioning scheme, with all moduleoutputs registered and with modules roughly of theoutputs registered and with modules roughly of thesame size.same size.

Make RTL code easy to understand, by using Make RTL code easy to understand, by using comments, meaningful names and consistent orcomments, meaningful names and consistent orparameters instead of hardparameters instead of hard --coded numberscoded numbers


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General Naming ConventionsGeneral Naming Conventions RuleRule : Develop Naming Convention: Develop Naming Convention

ConsistentConsistent DocumentationDocumentation

GuidelineGuideline Lower case : signal, variable and portLower case : signal, variable and port Uppercase : constant, user define typeUppercase : constant, user define type

type BUS_BYTE istype BUS_BYTE is std_logic_vectorstd_logic_vector ( 7( 7 downtodownto 0)0) sig_Asig_A : BUS_BYTE;: BUS_BYTE;

Short but descriptive namesShort but descriptive names Clock :Clock : clkclk oror clk1clk1 , , clk_interface clk_interface The same clock name for the same The same clock name for the same clkclk sourcesource Active low signal : Active low signal : _b _b oror _n _n Reset :Reset : rst rst oror rst_n rst_n ConsistentConsistent MultibitMultibit description : (y description : (y downtodownto x) and (x to y)x) and (x to y) Recommended :Recommended : (y (y downtodowntox)x) oror (x:0)(x:0) Use the same name or similar name for port and signals:Use the same name or similar name for port and signals:

(a=>a; a=>(a=>a; a=> a_int a_int ) )


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Signal Naming ConventionsSignal Naming Conventions

Tristate Tristate internal signalinternal signal*_z*_z

Data before being registered into a registerData before being registered into a register with the same name with the same name

*_ *_ nxtnxt

Signal inSignal in n n - - thth phasephase*_ *_ pnpn

Async Async signalsignal*_a*_a

Output of registersOutput of registers*_r*_r


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Architecture Naming Convention Architecture Naming Convention

ARCITECTURE ARCITECTURE simsim OF my_behave_model ISOF my_behave_model IS

oror ARCITECTURE ARCITECTURE tbtb OF my_test_bench ISOF my_test_bench IS

SimulationSimulation

ModelModel

ARCITECTURE ARCITECTURE rtlrtl OFOF my_syn_modelmy_syn_model ISIS

oror ARCITECTURE ARCITECTURE strstr OF my_structural_design ISOF my_structural_design IS

SynthesisSynthesis

ModelModel


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Include Header in Source FilesInclude Header in Source Files RuleRule

Filename, AuthorFilename, Author Function and key featuresFunction and key features

Date createdDate created Modification History : date, name,Modification History : date, name, descdesc of changesof changes


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Use CommentsUse Comments RuleRule

Explain all process,Explain all process,function, declaration of function, declaration of types and subtypestypes and subtypes

Guidelines:Guidelines: Use comments toUse comments toexplains ports, signals,explains ports, signals,

and variables, or groupsand variables, or groupsof signalsof signals

ContohContoh ::

---- VHDL CodeVHDL Code ----

signalsignal mySignal mySignal :: std_logic std_logic ;;

---- an example signalan example signal

MYsignal MYsignal


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Keep Commands on Separate LinesKeep Commands on Separate Lines

RuleRule Use separate line for each VHDL statementUse separate line for each VHDL statement

(readable and maintainable)(readable and maintainable)

Line LengthLine Length GuidelineGuideline

Keep line length to 72 char or lessKeep line length to 72 char or less


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IndentionIndention RuleRule

Use indention to improve the readability of continued codeUse indention to improve the readability of continued codelines and nested loopslines and nested loops if if if if

end if;end if; end if;end if;

GuidelinesGuidelines Use 2 spaceUse 2 space

GuidelinesGuidelines Avoid using tabs Avoid using tabs


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Do not Use HDL Reserved WordsDo not Use HDL Reserved Words RuleRule

Do not use nether VHDL orDo not use nether VHDL or Verilog Verilog reserved word.reserved word.Because they are going to be translatedBecause they are going to be translated


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Port OrderingPort Ordering Rule:Rule:

Declare ports in a logical order, and keep consistentDeclare ports in a logical order, and keep consistent

GuidelineGuideline Declare one port per line, with a comment following itDeclare one port per line, with a comment following it Inputs:Inputs:

ClocksClocks ResetsResets

EnablesEnables Other Control SignalsOther Control Signals Data and address linesData and address lines

Outputs:Outputs: ClocksClocks ResetsResets EnablesEnables Other Control SignalsOther Control Signals DataData


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Port Maps and Generic MapsPort Maps and Generic Maps Rule:Rule:

Use explicit mapping, using named association ratherUse explicit mapping, using named association ratherthan positional associationthan positional association

GuidelineGuideline Leave blank line between the input and output portsLeave blank line between the input and output ports

to improveto improve readibility readibility


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5.4 Guideline for Clocks & Reset5.4 Guideline for Clocks & Reset Preferred : single global clock and positive edgePreferred : single global clock and positive edge--

triggeredtriggered

D Q

Clock

D D Q Q


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5.4.1 Avoid Mixed Clock Edges5.4.1 Avoid Mixed Clock Edges Guideline: Avoid using both positive and negativeGuideline: Avoid using both positive and negative --edgeedge

triggered fliptriggered flip--flopsflops Cautions in mixed clock edge:Cautions in mixed clock edge: The duty cycle becomes a critical The duty cycle becomes a critical ScanScan--based testing methodologies require separate handling based testing methodologies require separate handling

Separate them into different module. Put them inSeparate them into different module. Put them indifferent scan chainsdifferent scan chains

Rule:Rule: Be sure to model the worst case duty cycle ( Be sure to model the worst case duty cycle ( synthsynth & timing & timing

analysis)analysis) Document the assumed duty cycleDocument the assumed duty cycle


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Avoid Mixed Clock Edge Avoid Mixed Clock Edge

D Q

Clock

D D Q Q


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5.4.2 Avoid Clock Buffers5.4.2 Avoid Clock Buffers G: Avoid hand instantiating clock buffers inG: Avoid hand instantiating clock buffers in

RTL code.RTL code. Part of physical designPart of physical design


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5.4.4 Avoid Internally Generated Clocks5.4.4 Avoid Internally Generated Clocks

G: Avoid using internally generated clocksG: Avoid using internally generated clocks Cause limited testability : cannot be part of scanCause limited testability : cannot be part of scan

chainchain Difficult to put constrain for synthesisDifficult to put constrain for synthesis

Alternative: Alternative:

Design synchronous designDesign synchronous design Use multiple clocksUse multiple clocks


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5.4.5 Gated Clock and Low Power Design5.4.5 Gated Clock and Low Power Design Guideline:Guideline:

Keep the clock and/or reset generation circuitry as a separateKeep the clock and/or reset generation circuitry as a separatemodule at top level of the design.module at top level of the design. Partition the design so that all the logic in a single module usPartition the design so that all the logic in a single module us ee

a single clock and single reset.a single clock and single reset.

Gated clock should never occur within a macro.Gated clock should never occur within a macro. Gated clock should appear at top level of the designGated clock should appear at top level of the design

hierarchy.hierarchy. Standard timing analysis and scan chain can be applied toStandard timing analysis and scan chain can be applied to

each module.each module. See Example 5See Example 5--1717


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5.4.6 Avoid Internally Generated Reset5.4.6 Avoid Internally Generated Reset

Make sure registers are controlled only by a simple resetMake sure registers are controlled only by a simple reset

signalsignal G: Avoid internally generated, conditional resets : makeG: Avoid internally generated, conditional resets : make

analysis and design much simpler and easieranalysis and design much simpler and easier

G: if conditional reset required, create separate signal,G: if conditional reset required, create separate signal,and isolate inand isolate in saparatesaparate module (increase readable andmodule (increase readable andsyntheisissyntheisis result)result)

See Example 5See Example 5--1818


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5.5 Coding for Synthesis5.5 Coding for Synthesis Best compile and synthesis resultBest compile and synthesis result Testability Testability PerformancePerformance

Simplification of static timing analysisSimplification of static timing analysis GateGate --level circuitlevel circuit behaviourbehaviour thatthat machesmaches that of that of

the original RTL codethe original RTL code


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5.5.2 Avoid Latches5.5.2 Avoid Latches Exception: instantiate technology Exception: instantiate technology --independent GTECH.D.independent GTECH.D.

Provide list of documentation and its special timing requirementProvide list of documentation and its special timing requirement ss Note: check latches = all_registersNote: check latches = all_registers level_sensitivelevel_sensitive VHDL code infers latches: example 5 VHDL code infers latches: example 5 --21, 521, 5--2222 G: avoid latchG: avoid latch

Assign default values at the beginning of a process (Example 5 Assign default values at the beginning of a process (Example 5 --24)24) Assign outputs for all input conditions (Example 5 Assign outputs for all input conditions (Example 5 --25)25) Use else (instead of Use else (instead of elsif elsif ) for the final priority branch (example 5 ) for the final priority branch (example 5 --26)26)


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5.5.3 If latch must be used5.5.3 If latch must be used Testability: Use a Testability: Use a muxmux to provide either theto provide either the

normal function or the input from an I/O padnormal function or the input from an I/O padas data toas data to muxmux See Figure 5See Figure 5--77


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Avoid Combinational Feedback Avoid Combinational Feedback

A

BC

D Q Q


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5.5.5 Specify Complete Sensitivity Lists5.5.5 Specify Complete Sensitivity Lists Pre and post layout may differPre and post layout may differ

See Figure 5See Figure 5--99 Combinational block Combinational block

Must include all signals read by processMust include all signals read by process Example 5Example 5--2727

Sequential block Sequential block Include clock and reset signalInclude clock and reset signal Example 5Example 5--2828

Must not include unnecessary sensitivity list. It may Must not include unnecessary sensitivity list. It may slow down simulationslow down simulation


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2.2.10 Process2.2.10 ProcessContohContoh ::

entityentity AND_OR_XOR AND_OR_XOR isis port port (A,B(A,B :: inin bit; bit;

Z_OR, Z_AND, Z_XOR Z_OR, Z_AND, Z_XOR ::outout bit); bit);end end AND_OR_XOR; AND_OR_XOR;

architecturearchitecture RTLRTL ofof AND_OR_XOR AND_OR_XOR isis

begin begin A_O_X: A_O_X: process process (A, B)(A, B) begin begin

Z_OR Z_OR


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Sequential Logic: DSequential Logic: D --Flip FlopFlip Flop

architecture rtl of D_FF isarchitecture rtl of D_FF isarchitecture rtl of D_FF isarchitecture rtl of D_FF isbeginbeginbeginbeginprocess (Clock, Reset) isprocess (Clock, Reset) isprocess (Clock, Reset) isprocess (Clock, Reset) isbeginbeginbeginbegin

if Reset =if Reset =if Reset =if Reset = 1111 thenthenthenthenQ


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Blocking and NonBlocking and Non --blockingblocking Assignments ( Assignments ( Verilog Verilog ))

Blocking: execute in sequential orderBlocking: execute in sequential order

NonNon --Blocking : execute concurrently Blocking : execute concurrently Use blocking statement inside alwaysUse blocking statement inside always

@( @( posedgeposedge clk clk ) ) Example 5Example 5--29, 529, 5--3030


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SignalSignal vs vs Variable Variable Signal: scheduled to be executed in nextSignal: scheduled to be executed in next

simulation clock cyclesimulation clock cycle Variable: take effect immediately Variable: take effect immediately

Guideline : use signal instead of variableGuideline : use signal instead of variable See Example 5See Example 5--3131


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Sequential Logic: DSequential Logic: D --Flip FlopFlip Floparchitecture rtl of D_FF is

begin process (Clock) is begin

if (Clockevent and Clock=1) thenif Reset = 1 then

S1


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Case vs. if then elseCase vs. if then else Case : single level multiplexerCase : single level multiplexer

If If --thenthen --else: priority encoded, cascadedelse: priority encoded, cascadedcombination of combination of muxmux

See Figure 5See Figure 5--12, 512, 5--1313 Guideline: multiplexer is faster circuit. Use caseGuideline: multiplexer is faster circuit. Use casestatement rather than an if statement rather than an if --thenthen --elseelse

Conditional assignment also infer aConditional assignment also infer a muxmux See example 5See example 5--3434


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Coding State MachinesCoding State Machines Separate the state machine HDLSeparate the state machine HDL descdesc into twointo two

process, combination and sequential logicprocess, combination and sequential logic Create enumerated type for the state vectorCreate enumerated type for the state vector Keep FSM logic and nonKeep FSM logic and non --FSM logic in separateFSM logic in separate

modulesmodules Assign a default state for the state machine. Assign a default state for the state machine.

Implement idle state. Assign a state for otherImplement idle state. Assign a state for othercondition (Example 5condition (Example 5 --35, 535, 5--36).36).


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5.6 Partition for Synthesis5.6 Partition for Synthesis Advantages: Advantages:

Better synthesis resultBetter synthesis result Faster compile runtimeFaster compile runtime Ability to use simpler Ability to use simpler synthsynth strategy to meet timing strategy to meet timing


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Register All OutputsRegister All Outputs Simplify the synthesis processSimplify the synthesis process

Makes output drive strengths (flipMakes output drive strengths (flip --flop) andflop) andinput delay predictableinput delay predictable

All input of each block arrive the same relative All input of each block arrive the same relativedelay delay Figure 5Figure 5--14 example of registered output14 example of registered output

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