308 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 2, FEBRUARY 2002

Threshold Voltage Roll-Up/Roll-Off CharacteristicControl in Sub-0.2-�m Single Workfunction GateCMOS for High-Performance DRAM Applications

Satoshi Inaba, Member, IEEE, Ryota Katsumata, Hiroyuki Akatsu, Rajesh Rengarajan, Paul Ronsheim,Cheruvu S. Murthy, Kazumasa Sunouchi, Member, IEEE, and Gary B. Bronner, Member, IEEE

Abstract—Threshold voltage ( ) roll-off/roll-up control is akey issue to achieve high-performance sub-0.2-m single work-function gate CMOS devices for high-speed DRAM applications.It is experimentally confirmed that a combination of well RTA andN2 implant prior to gate oxidation is important to reduce roll-upcharacteristics both in nFET and pFET. Optimization of RTA con-ditions after source/drain (S/D) implant is also discussed as a meansof improving roll-off characteristics. Finally, the impact of haloimplant on variation in sub-0.2- m buried channel pFETs isdiscussed. It is found that halo profile control is necessary for tight

variation in sub-0.2- m single workfunction gate pFET.

Index Terms—Buried channel, halo structure, MOSFETs, N2implant, pFET, silicon, single workfunction gate, variation, wellRTA.

I. INTRODUCTION

I N recent sub-0.2-m generation DRAMs, higher perfor-mance support devices are required in peripheral circuits to

achieve high-speed operation, especially for applications suchas synchronous DRAMs (SDRAMs) meeting PC133 MHz2-2-2 specifications or later [1], [2]. Even in sub-0.2-m era,single workfunction gate CMOS technology still has a keyrole in commodity DRAMs because of its simple process andhigher thermal budget immunity in buried channel pFETs (i.e.,no boron penetration from the gate electrode). Therefore, itis a very challenging thing to achieve technological advancesin support device in sub-0.2-m generation DRAM and be-yond. Required support device performance is not restrictedto high current drive. Threshold voltage characteristiccontrol is also required such as the minimization of both

roll-off/roll-up; i.e., short-channel effect (SCE)/reverseshort-channel effect (RSCE) in -Lpoly relationships. Theminimization of variation at nominal gate length is alsoimportant for DRAM products.

Manuscript received January 17, 2001; revised October 23, 2001. The reviewof this paper was arranged by Editor K. Shenai.

S. Inaba, R. Katsumata, and K. Sunouchi were with Toshiba-IBM R&DCenter, Toshiba America Electronic Components, Inc., at DRAM DevelopmentAlliance, IBM Z33A, Hopewell Junction, NY 12533 USA. They are now withToshiba Corporation Semiconductor Company, Yokohama 235-8522, Japan(e-mail: satoshi1.inaba@toshiba.co.jp).

H. Akatsu, P. Ronsheim, C. S. Murthy, and G. B. Bronner are with Semicon-ductor R&D Center, IBM Microelectronics, at DRAM Development Alliance,IBM Z33A, Hopewell Junction, NY 12533 USA.

R. Rengarajan is with Infineon Technologies AG, at DRAM DevelopmentAlliance, IBM Z33A, Hopewell Junction, NY 12533 USA.

Publisher Item Identifier S 0018-9383(02)00648-2.

Fig. 1. Process integration flow for sub-0.2-�m single workfunction gateCMOS.

In this paper, characteristic control schemes for sub-0.2- m single workfunction gate CMOS are discussed fromthe view point of high-performance DRAM applications. Threetopics will be discussed through experimental results:

1) channel impurity profile control to have less roll-offand roll-up;

2) source/drain (S/D) extension profile control to achieveless SCE;

3) possible root cause of variation in single workfunctiongate pFET.

II. DEVICE FABRICATION AND EXPERIMENTS

A series of single workfunction gate CMOS devices down to0.18 m gate length (drawn) were fabricated on Si (100) wafersby 0.175 m trench DRAM integration process. The fabricationprocess flow is shown in Fig. 1.

Some samples were implanted with Nprior to gate oxida-tion to study the impact of thinning the oxide thickness [3].A thin SiN gate sidewall spacer was formed after nS/D ex-tension implant, while both pS/D extension and halo implantwere performed from the outside of this SiN sidewall spacer [4].Several options for improving roll-off characteristics were

0018–9383/02$17.00 © 2002 IEEE

INABA et al.: THRESHOLD VOLTAGE ROLL-UP/ROLL-OFF CHARACTERISTIC CONTROL 309

evaluated. For example, some samples were exposed to germa-nium preamorphization implant (Ge PAI) before pextensionimplant to control S/D extension depth in pFET region [5]. Theresults will be discussed in the following sections.

The depth profiles of channel impurity concentration wereobtained by secondary ion mass spectroscopy (SIMS). The im-purity profiles in S/D extensions were also investigated by SIMSto confirm the reason of different SCE with different RTA con-ditions.

III. CHANNEL PROFILE CONTROL BY WELL RTAAND N IMPLANT

Reduction of roll-off is the most important issue for allscaled CMOS devices, especially for sub-0.2-m ground ruleDRAM applications. On the other hand, the methodology forreduction of roll-up has not been fully discussed yet. Re-cent halo structure (pocket structure) for S/D extensions has al-lowed considerable improvement in SCE suppression. However,it inevitably causes RSCE ( roll-up) in the short-channelregion. due to the modulation of substrate impurity concentra-tion by halo implant itself and the transient enhanced diffusion(TED) of well/channel impurity, which was caused by S/D im-plant damage. roll-up is particularly undesirable for DRAMsupport device in peripheral circuit, because the sense ampli-fier circuit can only tolerate small mismatch caused by thevariation of gate length. In general, CMOS devices for analogcircuit applications also should have lessroll-up than thosefor digital circuit. It is expected that RTA just after well/channelimplant would be useful to recover the implant damage and tosuppress TED of well/channel impurities during gate oxidation[6]. Therefore, well RTA was applied to CMOS devices in pe-ripheral circuits of 256-Mb DRAM. Fig. 2(a) and (b) show typ-ical roll-off curves for nFET and pFET at saturation condi-tion, respectively. As expected, roll-up was reduced in nFETby well RTA. However, at long channel was increased innFET, and decreased in pFET by well RTA. It was also foundthat roll-up reduction was not enough for pFET. This couldbe caused by higher boron concentration near the surface, as aresult of preventing boron TED by well RTA [6].

Next, N implanted samples in the channel region before gateoxidation were investigated to see the impact of nitrogen onboron impurity profile. Fig. 3(a) and (b) show roll-off curvesfor nFET and pFET with Nimplant, respectively. In these sam-ples, roll-up was well suppressed and long-channel ’swere not changed regardless of well RTA both in nFET andpFET. ’s in long-channel nFET and pFET in Fig. 3 weresimilar to ’s in without well RTA case in Fig. 2. These phe-nomena suggest that implanted nitrogen would affect boron pro-file and activation in the channel region.

Fig. 4 shows the results of SIMS analysis for channel regionin pFET. It shows that the peak boron concentration is a little bithigher in the sample with well RTA than in the sample of withoutwell RTA for normal gate oxidation case (i.e., with no Nim-plant). This result suggests that out-diffusion of boron duringgate oxidation should not be ignored in the case of without wellRTA. On the other hand, in Nimplanted samples, there is al-most no difference in channel boron concentration at the sur-

(a)

(b)

Fig. 2. V –L relationships for (a) nFET and (b) pFET (without Nimplant).Solid line shows with well RTA case, dashed line shows without well RTA case.Well RTA suppressedV roll-up in nFET, however muchV discrepancy evenin the long-channel region has been observed.jV j reduction in pFET also hasbeen observed.

face, regardless of the presence or absense of well RTA. As aresult, roll-up was successfully reduced for both nFET andpFET by the combination of well RTA and Nimplant beforegate oxidation. Therefore, the importance of well RTA and Nimplant on roll-off/roll-up characteristic control was con-firmed in sub-0.2- m single workfunction gate CMOS for thefirst time.

IV. SOURCE/DRAIN IMPURITY PROFILE CONTROL

BY RTA OPTIMIZATION

Reduction of TED of S/D or halo dopants is also a key forthe control of roll-off and roll-up, especially in sub-0.2-mburied channel pFET [7]. To prevent TED of boron during sub-sequent thermal processing, such as gate sidewall formation orborophosphosilicate glass (BPSG) deposition, the impact of S/DRTA just after ion implant was investigated [8]. Fig. 5(a) and (b)show roll-off characteristics in both nFETs and pFETs withdifferent S/D RTA temperature, respectively. They also experi-enced final activation RTA (950C, 10 s). By comparing witheach other, the different S/D RTA temperature dependence ofroll-offs were found out between nFETs and pFETs.

In pFET case, higher temperature RTA causes worseroll-off/roll-up, though it may reduce the sheet resistance in pS/D.

310 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 2, FEBRUARY 2002

(a)

(b)

Fig. 3. V –L relationships for (a) nFET and (b) pFET (with Nimplant).Solid line shows with well RTA case, dashed line shows without well RTA case.V roll-up is well suppressed by Well RTA There is almost no difference inlong-channelV regardless of well RTA both in nFET and pFET.

Fig. 6 shows the final boron SIMS profile in pS/D region.It shows that boron diffusion is reduced by 800C RTA com-pared to the case of higher temperature RTA. For sub-0.2-mburied channel pFET, the reduction of roll-off has top pri-ority for chip size reduction, therefore lower temperature RTAshould be applied to reduce boron diffusion. Actually, in termsof parasitic resistance in pFET, about 15% sheet resistance in-crease was observed in 800C RTA case, compared to 1000CRTA case. However, there was no significant impact on the cur-rent drive at nominal effective gate length , due to relativelyhigher channel resistance in m region.

In nFET case, roll-off seems to be smaller with highertemperature S/D RTA than with lower temperature RTA. Asshown in Fig. 5(a), roll-off/roll-up seems to be the trade-offwith RTA temperature. This result suggest that arsenic TED issuppressed with high-temperature RTA. Fig. 7 shows the SIMSprofile for arsenic with different RTA temperature which indi-cates that higher temperature RTA remarkably improves junc-tion depth in nFET.

It is also expected in nFET that deeply implanted halo borondoes not diffuse enough toward the surface during the lowertemperature RTA. In the case of the higher temperature RTA,boron does diffuse to the surface enough to prevent SCE; How-ever too much thermal budget (high-temperature RTA) causes

roll-up and Arsenic diffusion in nFET S/D, even in the case of

(a)

(b)

Fig. 4. Boron and Arsenic profiles in pFET channel region. (a) Without Nimplant case, peak boron concentration is increased by well RTA. (b) With Nimplant case, there is almost no difference in peak boron profile at the vicinityof the surface.

N implant. Fig. 8 shows the results of gate overlap capacitance(Cov) measurement which support the above explanation. FornFET, lower temperature RTA results in large Cov that meanslarger lateral gate overlap length of S/D diffusion layer. As RTAtemperature increases, Cov decreases with nextension depthdecrease caused by halo boron diffusion to surface channel re-gion. In pFET, steady Cov increase suggests large boron diffu-sion with higher RTA temperature. We have found that to reduceboth roll-off/roll-up, the optimal S/D RTA temperature fornFET should be around 900–950C, while in the case of pFETdevices, an 800C RTA is optimal.

V. VARIATION CONTROL IN SUB-0.2- mBURIED CHANNEL pFET

Finally, we would like to discuss the control scheme ofvariation in single workfunction gate CMOS. Minimizingvariation at nominal gate length is very important for DRAM

INABA et al.: THRESHOLD VOLTAGE ROLL-UP/ROLL-OFF CHARACTERISTIC CONTROL 311

(a)

(b)

Fig. 5. V roll-offs in (a) nFET and in (b) pFET, respectively.V roll-off inpFET is improved with 800 C RTA, while V roll-off/ roll-up in nFET isimproved with 900–950 C RTA.

Fig. 6. Boron SIMS profile in p S/D extension region with different S/D RTAtemperature. An 800C 10 s RTA prevents boron diffusion compared to muchhigher RTA temperature case.

products as well as roll-off/roll-up control. In our experi-ments, thin SiN gate sidewall spacer was introduced before pimplant to adjust lateral boron diffusion [4]. However, even in

Fig. 7. Arsenic SIMS profile in n S/D extension region with different S/DRTA temperature. In case of 800C 10 s RTA, Arsenic TED has been observed.Junction depth becomes shallower with much higher temperature RTA.

Fig. 8. Gate overlap capacitance in nFET and pFET with different S/D RTAtemperature. Trade-off of halo boron diffusion and S/D diffusion is observed innFET case. Steady Cov increase in pFET suggests that large boron diffusion inS/D with higher temperature RTA.

Fig. 9. Difference of S/D implant in nFET and pFET in the sample. Boron andhalo implant were done from outside of thin SiN sidewall spacer in pFET.

the long-channel region, variation in buried channel pFETsseemed to be larger than that in nFETs in which ions were im-planted without SiN sidewall spacer. (see Fig. 9)

312 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 2, FEBRUARY 2002

Fig. 10. Comparison ofV variation in nFET and pFET at long-channel region.V variation in pFET is about two times larger than in nFET.

Fig. 11. Comparison ofV variation with/without self-alinged S/D extensionimplant at nominal gate length region. (L � 0:19 �m)V variation in pFETis reduced with self-alinged implant and Ge PAI process.

Fig. 10 shows the typical variations both in nFET andpFET. It clearly shows about two times larger variation inpFET than in nFET.

One possible explanation for this result is that the variationof SiN sidewall shape could affect S/D and halo implant, re-sulting in much variation of the two-dimentional impurity pro-file near S/D in the buried channel pFETs. To test this hypoth-esis, we looked at the impact of self-aligned pimplant beforeSiN sidewall spacer formation. We fabricated another sample inwhich S/D extensions were implanted without thin SiN sidewallspacer.

To control the junction depth and to eliminate the “halo” ef-fects, germanium (Ge) preamorphization implant (PAI) was ap-plied without any halo implants in pFETs [5]. Fig. 11 showsthe variation in short-channel region for Ge preamorphizedsample without thin SiN sidewall formation and halo implant.As expected, the sample with self-aligned pimplant showssmaller variation, even though this pFET has smaller andlarger Cov. This result may be due to well controlled S/D pro-file and absense of halo dopant fluctuation in single work func-tion gate pFET. Therefore, the tight control of both SiN side-wall spacer formation and S/D and halo implant process should

be essential for minimizing variation and Cov in sub-0.2-mburied channel pFETs.

VI. CONCLUSION

roll-off/roll-up control in sub-0.2-m single workfunc-tion gate CMOS has been successfully achieved for high-perfor-mance DRAM applications by Nimplant and well RTA opti-mization. It has been found that S/D RTA just after extension im-plant should be carefully and independently optimized in nFETand pFET to reduce TED during following thermal process.variation in buried channel pFETs has been found to be depen-dent on the variation of S/D and halo dopant profiles due to vari-ation in the physical structure of gate poly-Si and gate sidewallspacer. It can be improved either by tight process control on thephysical structure of gate electrode or by S/D process optimiza-tion.

ACKNOWLEDGMENT

The authors would like to thank H.-O. Joachim, Y. Matsubara,Y. Takegawa, M. Weybright, M. Aoki, A. Sudo, T. Hughes, Q.Ye, Y. Li, S.-F. Huang, W.-T. Kang, M. Dellow, W. Ellis, M. Ja-cunski, R. Longo, R. Srinivasan, R. Divakaruni, J. Alsmeier, andT. Mii for their helpful discussions. The authors also thank allmembers of DRAM Development Alliance between IBM/Infi-neon/Toshiba and the members of the Advanced SemiconductorTechnology Center (ASTC) at IBM Microelectronics for theirkind help and support throughout this work.

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[3] L. K. Han, S. Crowder, M. Hargrove, E. Wu, S. H. Lo, F. Guarin, E.Crabbé, and L. Su, “Electrical characteristics and reliability of sub-3-nmgate oxides grown on nitrogen implanted silicon substrates,” inIEDMTech. Dig., 1997, pp. 643–646.

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[8] M. Rodder, S. Aur, and I. C. Chen, “A scaled 1.8-V, 0.18-�m gate lengthCMOS technology: Device design and reliability considerations,” inIEDM Tech. Dig., 1995, pp. 415–418.

INABA et al.: THRESHOLD VOLTAGE ROLL-UP/ROLL-OFF CHARACTERISTIC CONTROL 313

Satoshi Inaba(M’98) was born in Kanagawa, Japan, in 1964. He received theB.S. degree in applied physics in 1988, and the M.S. degree in physics in 1990from Waseda University, Tokyo, Japan.

In 1990, he joined the ULSI Research Center, Toshiba Corporation,Kawasaki, where he has been engaged in the research and development ofdeep-submicrometer MOSFETs including 0.10-�m CMOS. In October 1994,He moved to the Semiconductor Device Engineering Laboratory and waswith ULSI Device Engineering Laboratory, Microelectronics EngineeringLaboratory, Toshiba Corporation, Yokohama, Japan, from 1996 to 1998.In August, 1998, he joined IBM-Siemens-TOSHIBA 256 Mb DRAM De-velopment Alliance (DDA), Hopewell Junction, NY, and worked both for0.175-�m/0.15-�m DRAM support device design in Device Design andCharacterization team (DDC). Since April 2000, he has been a Memberof System LSI Research and Development Center, Toshiba CorporationSemiconductor Company, Yokohama Japan. His current research interests arethe device physics and fabrication technology of high-speed and low-powerdissipation sub-50-nm CMOS devices. He is also interested in the physics ofelectron transport phenomena in the very small silicon devices.

Mr. Inaba is a Member of the Physical Society of Japan and the Japan Societyof Applied Physics.

Ryota Katsumatawas born in Kanagawa, Japan, in 1967. He received the M.S.degree in 1991 and the Ph.D in 1994 in applied physics from Tsukuba Univer-sity, Ibaraki, Japan.

He joined the ULSI Research Center, Toshiba Corporation, Kawasaki, Japan,in 1994, where he has been engaged in the research and development of low-kdielectric for multilevel interconnect using plasma CVD technique, In February1998, he joined IBM-Siemens-TOSHIBA 256 Mb DRAM Development Al-liance, Hopewell Junction, NY, and worked both for 0.175-�m/0.15-�m DRAMsupport device in Device Design and Characterization team. Since April 2000,he has been a Member of Advanced Memory Research and Development Center,Toshiba Corporation Semiconductor Company, Yokohama, Japan. His currentresearch interests are the device physics and fabrication technology of 0.11-�mDRAM.

Hiroyuki Akatsu received the Ph.D degree in electrical engineering fromWaseda University, Tokyo, Japan, in 1990.

He joined IBM Japan Tokyo Research Laboratory in 1990, where he workedon solid state disk card with Flash EEPROM. In 1993, he was assigned to IBMT. J. Watson Research Center, Yorktown Heights, NY, to work on the gate oxideprocess development and characterization, and then worked on wet cleaningprocess for DRAM fabrication. In 1996, he moved to IBM MicroelectronicsDivision, where he has been involved in wet process, array device design, andprocess integration of DRAM at Advanced Semiconductor Technology Centerin East Fishkill, NY. He also worked for technology transfer of DRAM to thefabs. He is currently a Senior Engineer at IBM Microelectronics’ SemiconductorResearch and Development Center, Hopewell Junction, NY.

Rajesh Rengarajanreceived the B.Tech. degree from the Indian Institute ofTechnology, Madras, in 1992, and the M.S. degree in electrical engineering fromthe University of Texas, Austin, in 1994.

He joined Texas Instruments Incorporated, Dallas, in 1994, where he workedin the area of quality and reliability of 0.35-�m CMOS devices. While at TexasInstruments, he also worked on process and device simulation of SOI CMOS de-vices. In 1997, he joined Siemens Microelectronics (now called Infineon Tech-nologies) working in the DRAM Development Alliance (DDA) with IBM andToshiba Corporation, Hopewell Junction, NY. He worked on development ofthe 0.35-�m, 0.25-�m, and 0.18-�m DRAM technologies and is currently man-aging Infineon’s Device Design group in the DDA. He is currently also involvedin the development of single workfunction devices for the 90-nm DRAM gen-eration.

Paul Ronsheimreceived the Ph.D. degree in materials science from the Uni-versity of Minnesota, in 1981.

He joined AT&T Bell Laboratories in 1981, where he worked on CMOS pack-aging reliability for telephone applications. In 1984, he moved to IBM’s Semi-conductor Development Laboratory, East Fishkill, NY, where he was involvedin bipolar device development using SIMS for device and materials character-ization. By the mid-1990’s, he was also involved in ultrashallow junction for-mation and characterization, and two-dimensional carrier imaging techniques.He has authored over 50 papers on materials characterization and holds sevenpatents. He is currently a Senior Technical Staff Member at IBM Microelec-tronics’ Semiconductor Research and Development Center.

Cheruvu S. Murthy received the M.S. degree in physics from the Indian In-stitute of Technology (IIT), Kanpur, and the Ph.D. degree in solid state physicsfrom the IIT, Madras.

He has held several postdoctoral positions in Europe and the U.S., which hasresulted in expertise in atomistic simulations for wide range of condensed phasephysical phenomena and chemical solutions. As a Research Scientist, he estab-lished research programs in modeling of interatomic interactions for semicon-ductors and metals and epitaxial growth simulations. He contributed to inter-disciplinary efforts of contract research related to high-energy density materialsand gas-surface processes. His career at IBM, since 1989, includes modelingof ion implantation, semiconductor process and device simulations for DRAMapplications, and atomistic studies of misfit dislocations and laser annealing.

Kazumasa Sunouchi(M’00) received the B.S. and M.S. degrees in materialscience from Tsukuba University, Ibaraki, Japan, in 1983 and 1985, respectively.

He joined the Toshiba VLSI Research Center, Kawasaki, Japan, in 1985,where he was engaged in the research and development of MOS memorydevices. He joined IBM-Siemens-Toshiba 256 Mb DRAM DevelopmentAlliance (DDA), Hopewell Junction, NY, in 1997 and managed Device Designand Characterization team (DDC). He is currently a Senior Specialist inAdvanced Memory Research and Developing Center, Toshiba CorporationSemiconductor Company, Yokohama, Japan, and managing high-performance100-nm node eDRAM developing group.

Mr. Sunouchi is a member of the Physical Society of Japan.

Gary B. Bronner (S’79–M’84) received the B.S. degree from Brown Univer-sity, Providence, RI, and the M.S. and the Ph.D. degrees from Stanford Univer-sity, Stanford, CA, all in electrical engineering. His thesis was on the getteringof metals in silicon.

In 1985, he joined the IBM T. J. Watson Research Center, Yorktown Heights,NY. He has worked on several generations of DRAM technology and was in-volved in research on advanced cell structures and processes. Other technicalinterests were selective epitaxy, gettering, and defects in silicon. He is currentlya Project Manager of DRAM Technology group at IBM Microelectronics’ Semi-conductor Research and Development Center, Hopewell Junction, NY.