UC3842B

HIGH PERFORMANCECURRENT MODECONTROLLERS

Order this document by UC3842B/D

D SUFFIXPLASTIC PACKAGE

CASE 751A(SO14)

N SUFFIXPLASTIC PACKAGE

CASE 626

D1 SUFFIXPLASTIC PACKAGE

CASE 751(SO8)

8

1

81

141

DeviceOperating

Temperature Range Package

ORDERING INFORMATION

UC384XBDUC384XBD1 TA = 0 to +70C

TA = 25 to +85C

SO14

UC384XBNUC284XBDUC284XBD1UC284XBNUC384XBVDUC384XBVD1UC384XBVN

TA = 40 to +105C

SO8PlasticSO14SO8PlasticSO14SO8Plastic

PIN CONNECTIONS

CompensationNC

Voltage FeedbackNC

Current SenseNC

RT/CT

CompensationVoltage Feedback

Current SenseRT/CT

Vref

VrefNCVCCVCOutputGndPower Ground

VCCOutputGnd

(Top View)

87

6

5

1

2

3

4

1

2

3

4

14

1312

11

5

67

1098

(Top View)

X indicates either a 2 or 3 to define specific device partnumbers.

1MOTOROLA ANALOG IC DEVICE DATA

The UC3842B, UC3843B series are high performance fixed frequencycurrent mode controllers. They are specifically designed for OffLine anddctodc converter applications offering the designer a costeffectivesolution with minimal external components. These integrated circuits featurea trimmed oscillator for precise duty cycle control, a temperaturecompensated reference, high gain error amplifier, current sensingcomparator, and a high current totem pole output ideally suited for driving apower MOSFET.

Also included are protective features consisting of input and referenceundervoltage lockouts each with hysteresis, cyclebycycle current limiting,programmable output deadtime, and a latch for single pulse metering.

These devices are available in an 8pin dualinline and surface mount(SO8) plastic package as well as the 14pin plastic surface mount (SO14).The SO14 package has separate power and ground pins for the totem poleoutput stage.

The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off), ideallysuited for offline converters. The UCX843B is tailored for lower voltageapplications having UVLO thresholds of 8.5 V (on) and 7.6 V (off). Trimmed Oscillator for Precise Frequency Control Oscillator Frequency Guaranteed at 250 kHz Current Mode Operation to 500 kHz Automatic Feed Forward Compensation Latching PWM for CycleByCycle Current Limiting Internally Trimmed Reference with Undervoltage Lockout High Current Totem Pole Output Undervoltage Lockout with Hysteresis Low Startup and Operating Current

Simplified Block Diagram

5.0VReference

LatchingPWM

VCCUndervoltage

Lockout

Oscillator

ErrorAmplifier

7(12)

VC7(11)Output

6(10)PowerGround

5(8)

3(5)CurrentSenseInput

Vref

8(14)

4(7)

2(3)

1(1)Gnd 5(9)

RT/CT

VoltageFeedback

Input

R

R

+

VrefUndervoltage

Lockout

OutputCompensation

Pin numbers in parenthesis are for the D suffix SO14 package.

VCC

Motorola, Inc. 1996 Rev 1

UC3842B, 43B UC2842B, 43B

2 MOTOROLA ANALOG IC DEVICE DATA

MAXIMUM RATINGSRating Symbol Value Unit

Total Power Supply and Zener Current (ICC + IZ) 30 mAOutput Current, Source or Sink (Note 1) IO 1.0 AOutput Energy (Capacitive Load per Cycle) W 5.0 JCurrent Sense and Voltage Feedback Inputs Vin 0.3 to + 5.5 VError Amp Output Sink Current IO 10 mAPower Dissipation and Thermal Characteristics

D Suffix, Plastic Package, SO14 Case 751AMaximum Power Dissipation @ TA = 25CThermal Resistance, JunctiontoAir

D1 Suffix, Plastic Package, SO8 Case 751Maximum Power Dissipation @ TA = 25CThermal Resistance, JunctiontoAir

N Suffix, Plastic Package, Case 626Maximum Power Dissipation @ TA = 25CThermal Resistance, JunctiontoAir

PDRJA

PDRJA

PDRJA

862145

702178

1.25100

mWC/W

mWC/W

WC/W

Operating Junction Temperature TJ +150 COperating Ambient Temperature

UC3842B, UC3843BUC2842B, UC2843BUC3842BV, UC3843BV

TA0 to + 70

25 to + 8540 to +105

C

Storage Temperature Range Tstg 65 to +150 C

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25C, for min/max values TA isthe operating ambient temperature range that applies [Note 3], unless otherwise noted.)

UC284XB UC384XB, XBV

Characteristics Symbol Min Typ Max Min Typ Max Unit

REFERENCE SECTIONReference Output Voltage (IO = 1.0 mA, TJ = 25C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 VLine Regulation (VCC = 12 V to 25 V) Regline 2.0 20 2.0 20 mVLoad Regulation (IO = 1.0 mA to 20 mA) Regload 3.0 25 3.0 25 mVTemperature Stability TS 0.2 0.2 mV/CTotal Output Variation over Line, Load, and Temperature Vref 4.9 5.1 4.82 5.18 VOutput Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25C) Vn 50 50 VLong Term Stability (TA = 125C for 1000 Hours) S 5.0 5.0 mVOutput Short Circuit Current ISC 30 85 180 30 85 180 mA

OSCILLATOR SECTIONFrequency

TJ = 25CTA = Tlow to ThighTJ = 25C (RT = 6.2 k, CT = 1.0 nF)

fOSC4948225

52

250

5556275

4948225

52

250

5556275

kHz

Frequency Change with Voltage (VCC = 12 V to 25 V) fOSC/V 0.2 1.0 0.2 1.0 %Frequency Change with Temperature

TA = Tlow to ThighfOSC/T 1.0 0.5 %

Oscillator Voltage Swing (PeaktoPeak) VOSC 1.6 1.6 VDischarge Current (VOSC = 2.0 V)

TJ = 25CTA = Tlow to Thigh (UC284XB, UC384XB)TA = Tlow to Thigh (UC384XBV)

Idischg7.87.5

8.3

8.88.8

7.87.67.2

8.3

8.88.88.8

mA

NOTES: 1. Maximum Package power dissipation limits must be observed.2. Adjust VCC above the Startup threshold before setting to 15 V.3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

Tlow = 0C for UC3842B, UC3843B Thigh = +70C for UC3842B, UC3843BTlow = 25C for UC2842B, UC2843B Thigh = +85C for UC2842B, UC2843BTlow = 40C for UC3842BV, UC3843BV Thigh = +105C for UC3842BV, UC3843BV

UC3842B, 43B UC2842B, 43B


ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25C, for min/max values TA isthe operating ambient temperature range that applies [Note 3], unless otherwise noted.)

UC284XB UC384XB, XBV


ERROR AMPLIFIER SECTIONVoltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 VInput Bias Current (VFB = 5.0 V) IIB 0.1 1.0 0.1 2.0 AOpen Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 65 90 dBUnity Gain Bandwidth (TJ = 25C) BW 0.7 1.0 0.7 1.0 MHzPower Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 60 70 dBOutput Current

Sink (VO = 1.1 V, VFB = 2.7 V)Source (VO = 5.0 V, VFB = 2.3 V)

ISinkISource

2.0 0.5

121.0

2.0 0.5

121.0

mA

Output Voltage SwingHigh State (RL = 15 k to ground, VFB = 2.3 V)Low State (RL = 15 k to Vref, VFB = 2.7 V)

(UC284XB, UC384XB) (UC384XBV)

VOHVOL

5.0

6.2

0.8

1.1

5.0

6.2

0.80.8

1.11.2

V

CURRENT SENSE SECTIONCurrent Sense Input Voltage Gain (Notes 4 & 5)

(UC284XB, UC384XB)(UC384XBV)

AV2.85

3.0

3.15

2.852.85

3.03.0

3.153.25

V/V

Maximum Current Sense Input Threshold (Note 4)(UC284XB, UC384XB)(UC384XBV)

Vth0.9

1.0

1.1

0.90.85

1.01.0

1.11.1

V

Power Supply Rejection RatioVCC = 12 V to 25 V, Note 4

PSRR 70 70 dB

Input Bias Current IIB 2.0 10 2.0 10 A

Propagation Delay (Current Sense Input to Output) tPLH(In/Out) 150 300 150 300 nsOUTPUT SECTIONOutput Voltage

Low State (ISink = 20 mA)(ISink = 200 mA) (UC284XB, UC384XB)

(UC384XBV)High State (ISource = 20 mA) (UC284XB, UC384XB)

(UC384XBV)(ISource = 200 mA)

VOL

VOH

13

12

0.11.6

13.5

13.4

0.42.2

1312.912

0.11.61.613.513.513.4

0.42.22.3

V

Output Voltage with UVLO ActivatedVCC = 6.0 V, ISink = 1.0 mA

VOL(UVLO) 0.1 1.1 0.1 1.1 V

Output Voltage Rise Time (CL = 1.0 nF, TJ = 25C) tr 50 150 50 150 nsOutput Voltage Fall Time (CL = 1.0 nF, TJ = 25C) tf 50 150 50 150 ns

UNDERVOLTAGE LOCKOUT SECTIONStartup Threshold (VCC)

UCX842B, BVUCX843B, BV

Vth157.8

168.4

179.0

14.57.8

168.4

17.59.0

V

Minimum Operating Voltage After TurnOn (VCC)UCX842B, BVUCX843B, BV

VCC(min)9.07.0

107.6

118.2

8.57.0

107.6

11.58.2

V

NOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V.3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

Tlow = 0C for UC3842B, UC3843B Thigh = +70C for UC3842B, UC3843BTlow = 25C for UC2842B, UC2843B Thigh = +85C for UC2842B, UC2843BTlow = 40C for UC3842BV, UC3843BV Thigh = +105C for UC3842BV, UC3843BV

4. This parameter is measured at the latch trip point with VFB = 0 V.5. Comparator gain is defined as: AV

V Output CompensationV Current Sense Input

UC3842B, 43B UC2842B, 43B


ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF, for typical values TA = 25C, for min/max values TAis the operating ambient temperature range that applies [Note 3], unless otherwise noted.)

UC284XB UC384XB, BV


PWM SECTIONDuty Cycle

Maximum (UC284XB, UC384XB)Maximum (UC384XBV)Minimum

DC(max)DC(min)

94

96

0

9493

9696

0

%

TOTAL DEVICEPower Supply Current

Startup (VCC = 6.5 V for UCX843B, Startup (VCC 14 V for UCX842B, BV)Operating (Note 2)

ICC + IC

0.3

12

0.5

17

0.3

12

0.5

17

mA

Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 30 36 VNOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V.

3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.Tlow = 0C for UC3842B, UC3843B Thigh = +70C for UC3842B, UC3843BTlow = 25C for UC2842B, UC2843B Thigh = +85C for UC2842B, UC2843BTlow = 40C for UC3842BV, UC3843BV Thigh = +105C for UC3842BV, UC3843BV

0.8

2.0

5.08.0

20

5080

R T, TI

MING

RES

ISTO

R (k

)

1.0 M500 k200 k100 k50 k20 k10 kfOSC, OSCILLATOR FREQUENCY (kHz)

VCC = 15 VTA = 25C

Figure 1. Timing Resistorversus Oscillator Frequency

Figure 2. Output Deadtimeversus Oscillator Frequency

1.0 M500 k200 k100 k50 k20 k10 kfOSC, OSCILLATOR FREQUENCY (kHz)

1.0

2.0

5.0

10

20

50

100

% D

T, PE

RCEN

T OUT

PUT D

EADT

IME

1

2

Figure 3. Oscillator Discharge Currentversus Temperature

Figure 4. Maximum Output Duty Cycleversus Timing Resistor

, DI

SCHA

RGE C

URRE

NT (m

A)

7.0 55

TA, AMBIENT TEMPERATURE (C) 25 0 25 50 75 100 125

disch

gI

7.5

8.0

8.5

9.0VCC = 15 VVOSC = 2.0 V

, MA

XIMU

M OU

TPUT

DU

TY CY

CLE

(%)

max

D 400.8

RT, TIMING RESISTOR (k)1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

50

60

70

80

90

100

Idischg = 7.5 mA

VCC = 15 VCT = 3.3 nFTA = 25C

1. CT = 10 nF2. CT = 5.0 nF3. CT = 2.0 nF4. CT = 1.0 nF5. CT = 500 pF6. CT = 200 pF7. CT = 100 pF

5

Idischg = 8.8 mA

7

3

6

4

VCC = 15 VTA = 25C

UC3842B, 43B UC2842B, 43B


Figure 5. Error Amp Small SignalTransient Response

Figure 6. Error Amp Large SignalTransient Response

Figure 7. Error Amp Open Loop Gain andPhase versus Frequency

Figure 8. Current Sense Input Thresholdversus Error Amp Output Voltage

Figure 9. Reference Voltage Changeversus Source Current

Figure 10. Reference Short Circuit Currentversus Temperature

20AVO

L, O

PEN

LOOP

VO

LTAG

E GA

IN (d

B)

10 M10f, FREQUENCY (Hz)

Gain

Phase

VCC = 15 VVO = 2.0 V to 4.0 VRL = 100 KTA = 25C

0

30

60

90

120

150

180100 1.0 k 10 k 100 k 1.0 M

0

20

40

60

80

100, EX

CESS

PHA

SE (D

EGRE

ES)

0VO, ERROR AMP OUTPUT VOLTAGE (V)

0

, CU

RREN

T SEN

SE IN

PUT T

HRES

HOLD

(V)

V th

0.2

0.4

0.6

0.8

1.0

1.2

2.0 4.0 6.0 8.0

VCC = 15 V

TA = 25C

TA = 55CTA = 125C

VCC = 15 V

TA = 55C

TA = 25C, REF

EREN

CE V

OLTA

GE C

HANG

E (m

V)

16

0Iref, REFERENCE SOURCE CURRENT (mA)

20 40 60 80 100 120

ref

V

12

8.0

4.0

0

20

24

TA = 125C

VCC = 15 VRL 0.1

, RE

FERE

NCE

SHOR

T CIR

CUIT

CURR

ENT (

mA)

SCI

50 55

TA, AMBIENT TEMPERATURE (C) 25 0 25 50 75 100 125

70

90

110

1.0 s/DIV0.5 s/DIV

20 m

V/DI

V

/

2.55 V

2.50 V

2.45 V

3.0 V

2.5 V

2.0 V

VCC = 15 VAV = 1.0TA = 25C

VCC = 15 VAV = 1.0TA = 25C

UC3842B, 43B UC2842B, 43B


Sink Saturation(Load to VCC)

TA = 55C

VCC

Source Saturation(Load to Ground)

0Vsa

t, OUT

PUT S

ATUR

ATIO

N VO

LTAG

E (V)

8000IO, OUTPUT LOAD CURRENT (mA)

200 400 600

1.0

2.0

3.0

2.0

1.0

0

TA = 55C

Figure 11. Reference Load Regulation Figure 12. Reference Line Regulation

Figure 13. Output Saturation Voltageversus Load Current Figure 14. Output Waveform

Figure 15. Output Cross Conduction Figure 16. Supply Current versus Supply Voltage

TA = 25C

RT = 10 kCT = 3.3 nFVFB = 0 VISense = 0 VTA = 25C

, SU

PPLY

CU

RREN

T (mA

)CCI

00

VCC, SUPPLY VOLTAGE (V)10 20 30 40

5

10

15

20

25

UCX8

43B

UCX8

42B

TA = 25C

Gnd

VCC = 15 V80 s Pulsed Load

120 Hz Rate

2.0 ms/DIV 2.0 ms/DIV

VCC = 15 VIO = 1.0 mA to 20 mATA = 25C

VCC = 12 V to 25 TA = 25C

, OU

TPUT

VO

LTAG

E CH

ANGE

(2.0 m

V/DIV)

V O

, OU

TPUT

VO

LTAG

E CH

ANGE

(2.0 m

V/DIV)

V O

VCC = 30 VCL = 15 pFTA = 25C

VCC = 15 VCL = 1.0 nFTA = 25C

50 ns/DIV

100 ns/DIV

100 m

A/DI

V20

V/D

IV

90%

10%

, OU

TPUT

VO

LTAG

EOV

, SU

PPLY

CU

RREN

TCCI

UC3842B, 43B UC2842B, 43B


PIN FUNCTION DESCRIPTION Pin

F i D i i8Pin 14Pin Function Description

1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.

2 3 VoltageFeedback

This is the inverting input of the Error Amplifier. It is normally connected to the switching powersupply output through a resistor divider.

3 5 CurrentSense

A voltage proportional to inductor current is connected to this input. The PWM uses thisinformation to terminate the output switch conduction.

4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed byconnecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHzis possible.

5 Gnd This pin is the combined control circuitry and power ground.

6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourcedand sunk by this pin.

7 12 VCC This pin is the positive supply of the control IC.

8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT.

8 PowerGround

This pin is a separate power ground return that is connected back to the power source. It is usedto reduce the effects of switching transient noise on thecontrol circuitry.

11 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separate powersource connection, it can reduce the effects of switching transient noise on the control circuitry.

9 Gnd This pin is the control circuitry ground return and is connected back to the power source ground.

2,4,6,13 NC No connection. These pins are not internally connected.

UC3842B, 43B UC2842B, 43B


OPERATING DESCRIPTIONThe UC3842B, UC3843B series are high performance,

fixed frequency, current mode controllers. They arespecifically designed for OffLine and dctodc converterapplications offering the designer a costeffective solutionwith minimal external components. A representative blockdiagram is shown in Figure 17.Oscillator

The oscillator frequency is programmed by the valuesselected for the timing components RT and CT. Capacitor CTis charged from the 5.0 V reference through resistor RT toapproximately 2.8 V and discharged to 1.2 V by an internalcurrent sink. During the discharge of CT, the oscillatorgenerates an internal blanking pulse that holds the centerinput of the NOR gate high. This causes the Output to be in alow state, thus producing a controlled amount of outputdeadtime. Figure 1 shows RT versus Oscillator Frequencyand Figure 2, Output Deadtime versus Frequency, both forgiven values of CT. Note that many values of RT and CT willgive the same oscillator frequency but only one combinationwill yield a specific output deadtime at a given frequency. Theoscillator thresholds are temperature compensated to within6% at 50 kHz. Also because of industry trends moving theUC384X into higher and higher frequency applications, theUC384XB is guaranteed to within 10% at 250 kHz. Theseinternal circuit refinements minimize variations of oscillatorfrequency and maximum output duty cycle. The results areshown in Figures 3 and 4.

In many noisesensitive applications it may be desirableto frequencylock the converter to an external system clock.This can be accomplished by applying a clock signal to thecircuit shown in Figure 20. For reliable locking, thefreerunning oscillator frequency should be set about 10%less than the clock frequency. A method for multiunitsynchronization is shown in Figure 21. By tailoring the clockwaveform, accurate Output duty cycle clamping can beachieved.

Error AmplifierA fully compensated Error Amplifier with access to the

inverting input and output is provided. It features a typical dcvoltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHzwith 57 degrees of phase margin (Figure 7). Thenoninverting input is internally biased at 2.5 V and is notpinned out. The converter output voltage is typically divideddown and monitored by the inverting input. The maximuminput bias current is 2.0 A which can cause an outputvoltage error that is equal to the product of the input biascurrent and the equivalent input divider source resistance.

The Error Amp Output (Pin 1) is provided for external loopcompensation (Figure 31). The output voltage is offset by twodiode drops (1.4 V) and divided by three before it connectsto the noninverting input of the Current Sense Comparator.This guarantees that no drive pulses appear at the Output(Pin 6) when pin 1 is at its lowest state (VOL). This occurswhen the power supply is operating and the load is removed,

or at the beginning of a softstart interval (Figures 23, 24).The Error Amp minimum feedback resistance is limited by theamplifiers source current (0.5 mA) and the required outputvoltage (VOH) to reach the comparators 1.0 V clamp level:

Rf(min) 3.0 (1.0 V) + 1.4 V0.5 mA = 8800

Current Sense Comparator and PWM LatchThe UC3842B, UC3843B operate as a current mode

controller, whereby output switch conduction is initiated bythe oscillator and terminated when the peak inductor currentreaches the threshold level established by the Error AmplifierOutput/Compensation (Pin 1). Thus the error signal controlsthe peak inductor current on a cyclebycycle basis. TheCurrent Sense Comparator PWM Latch configuration usedensures that only a single pulse appears at the Output duringany given oscillator cycle. The inductor current is convertedto a voltage by inserting the groundreferenced senseresistor RS in series with the source of output switch Q1. Thisvoltage is monitored by the Current Sense Input (Pin 3) andcompared to a level derived from the Error Amp Output. Thepeak inductor current under normal operating conditions iscontrolled by the voltage at pin 1 where:

Ipk =V(Pin 1) 1.4 V

3 RS

Abnormal operating conditions occur when the powersupply output is overloaded or if output voltage sensing islost. Under these conditions, the Current Sense Comparatorthreshold will be internally clamped to 1.0 V. Therefore themaximum peak switch current is:

Ipk(max) = 1.0 VRSWhen designing a high power switching regulator it

becomes desirable to reduce the internal clamp voltage inorder to keep the power dissipation of RS to a reasonablelevel. A simple method to adjust this voltage is shown inFigure 22. The two external diodes are used to compensatethe internal diodes, yielding a constant clamp voltage overtemperature. Erratic operation due to noise pickup can resultif there is an excessive reduction of the Ipk(max) clampvoltage.

A narrow spike on the leading edge of the currentwaveform can usually be observed and may cause the powersupply to exhibit an instability when the output is lightlyloaded. This spike is due to the power transformerinterwinding capacitance and output rectifier recovery time.The addition of an RC filter on the Current Sense Input with atime constant that approximates the spike duration willusually eliminate the instability (refer to Figure 26).

UC3842B, 43B UC2842B, 43B


+

ReferenceRegulator

VCCUVLO

+

VrefUVLO

3.6V

36V

S

RQ

InternalBias

+ 1.0mA

Oscillator

2.5VR

R

R

2R

ErrorAmplifier

VoltageFeedback

Input

Output/Compensation Current SenseComparator

1.0V

VCC 7(12)

Gnd 5(9)

VC

7(11)

Output

6(10)Power Ground

5(8)Current Sense Input

3(5) RS

Q1

VCC Vin

1(1)

2(3)

4(7)

8(14)

RT

CT

Vref

= Sink Only Positive True LogicPin numbers adjacent to terminals are for the 8pin dualinline package.Pin numbers in parenthesis are for the D suffix SO14 package.

Figure 17. Representative Block Diagram

Figure 18. Timing Diagram

Large RT/Small CT Small RT/Large CT

PWMLatch

(SeeText)

Capacitor CT

LatchSet Input

Output/Compensation

Current SenseInput

LatchReset Input

Output

UC3842B, 43B UC2842B, 43B


Undervoltage LockoutTwo undervoltage lockout comparators have been

incorporated to guarantee that the IC is fully functional beforethe output stage is enabled. The positive power supplyterminal (VCC) and the reference output (Vref) are eachmonitored by separate comparators. Each has builtinhysteresis to prevent erratic output behavior as theirrespective thresholds are crossed. The VCC comparatorupper and lower thresholds are 16 V/10 V for the UCX842B,and 8.4 V/7.6 V for the UCX843B. The Vref comparator upperand lower thresholds are 3.6 V/3.4 V. The large hysteresisand low startup current of the UCX842B makes it ideallysuited in offline converter applications where efficientbootstrap startup techniques are required (Figure 33). TheUCX843B is intended for lower voltage dctodc converterapplications. A 36 V zener is connected as a shunt regulatorfrom VCC to ground. Its purpose is to protect the IC fromexcessive voltage that can occur during system startup. Theminimum operating voltage (VCC) for the UCX842B is 11 Vand 8.2 V for the UCX843B.

These devices contain a single totem pole output stagethat was specifically designed for direct drive of powerMOSFETs. It is capable of up to 1.0 A peak drive current andhas a typical rise and fall time of 50 ns with a 1.0 nF load.Additional internal circuitry has been added to keep theOutput in a sinking mode whenever an undervoltage lockoutis active. This characteristic eliminates the need for anexternal pulldown resistor.

The SO14 surface mount package provides separatepins for VC (output supply) and Power Ground. Properimplementation will significantly reduce the level of switchingtransient noise imposed on the control circuitry. Thisbecomes particularly useful when reducing the Ipk(max) clamplevel. The separate VC supply input allows the designeradded flexibility in tailoring the drive voltage independent ofVCC. A zener clamp is typically connected to this input whendriving power MOSFETs in systems where VCC is greaterthan 20 V. Figure 25 shows proper power and control groundconnections in a currentsensing power MOSFETapplication.

ReferenceThe 5.0 V bandgap reference is trimmed to 1.0%

tolerance at TJ = 25C on the UC284XB, and 2.0% on theUC384XB. Its primary purpose is to supply charging currentto the oscillator timing capacitor. The reference has shortcircuit protection and is capable of providing in excess of20 mA for powering additional control system circuitry.Design Considerations

Do not attempt to construct the converter onwirewrap or plugin prototype boards. High frequencycircuit layout techniques are imperative to preventpulsewidth jitter. This is usually caused by excessive noisepickup imposed on the Current Sense or Voltage Feedbackinputs. Noise immunity can be improved by lowering circuitimpedances at these points. The printed circuit layout shouldcontain a ground plane with lowcurrent signal andhighcurrent switch and output grounds returning onseparate paths back to the input filter capacitor. Ceramicbypass capacitors (0.1 F) connected directly to VCC, VC,and Vref may be required depending upon circuit layout. Thisprovides a low impedance path for filtering the high frequencynoise. All high current loops should be kept as short as

possible using heavy copper runs to minimize radiated EMI.The Error Amp compensation circuitry and the converteroutput voltage divider should be located close to the IC andas far as possible from the power switch and othernoisegenerating components.

Current mode converters can exhibit subharmonicoscillations when operating at a duty cycle greater than 50%with continuous inductor current. This instability isindependent of the regulators closed loop characteristicsand is caused by the simultaneous operating conditions offixed frequency and peak current detecting. Figure 19Ashows the phenomenon graphically. At t0, switch conductionbegins, causing the inductor current to rise at a slope of m1.This slope is a function of the input voltage divided by theinductance. At t1, the Current Sense Input reaches thethreshold established by the control voltage. This causes theswitch to turn off and the current to decay at a slope of m2,until the next oscillator cycle. The unstable condition can beshown if a perturbation is added to the control voltage,resulting in a small I (dashed line). With a fixed oscillatorperiod, the current decay time is reduced, and the minimumcurrent at switch turnon (t2) is increased by I + I m2/m1.The minimum current at the next cycle (t3) decreases to (I +I m2/m1) (m2/m1). This perturbation is multiplied by m2/m1on each succeeding cycle, alternately increasing anddecreasing the inductor current at switch turnon. Severaloscillator cycles may be required before the inductor currentreaches zero causing the process to commence again. Ifm2/m1 is greater than 1, the converter will be unstable. Figure19B shows that by adding an artificial ramp that issynchronized with the PWM clock to the control voltage, theI perturbation will decrease to zero on succeeding cycles.This compensating ramp (m3) must have a slope equal to orslightly greater than m2/2 for stability. With m2/2 slopecompensation, the average inductor current follows thecontrol voltage, yielding true current mode operation. Thecompensating ramp can be derived from the oscillator andadded to either the Voltage Feedback or Current Senseinputs (Figure 32).

Control Voltage

InductorCurrent

Oscillator Period

Control Voltage

InductorCurrent

Oscillator Period

(A)

(B)

Figure 19. Continuous Current Waveforms

m1 m2

t0 t1 t2 t3

m3

m2

t4 t5 t6

I

m1I

l l m2m1l l m2

m1m2m1

UC3842B, 43B UC2842B, 43B


Figure 20. External Clock Synchronization Figure 21. External Duty Cycle Clamp andMultiUnit Synchronization

Figure 22. Adjustable Reduction of Clamp Level Figure 23. SoftStart Circuit

2(3) EA

Bias

+

Osc

R

R

R

2R

5(9)

1(1)

4(7)

8(14)

RT

CT

Vref

0.01

The diode clamp is required if the Sync amplitude is large enough to cause the bottomside of CT to go more than 300 mV below ground.

ExternalSyncInput

47

+

R

R

R

2R

Bias

Osc

EA

5(9)

1(1)

2(3)

4(7)

8(14)

To AdditionalUCX84XBs

R

S

Q

8 4

6

5

2

1

C

3

7

RA

RB 5.0k

5.0k

5.0kMC1455

f 1.44(RA 2RB)C D(max) RB

RA 2RB

+

5.0V Ref

+

S

RQ

Bias

+

Osc

R

R

R2REA

1.0V

5(9)

7(11)

6(10)

5(8)

3(5) RS

Q1

VCC Vin

1(1)

2(3)

4(7)

8(14)

R1

VClampR2

5.0V Ref

+

S

RQ

Bias

+

1.0mA

Osc

R

R

R2R

EA 1.0V

5(9)

1(1)

2(3)

4(7)

8(14)

C

1.0M

tSoftStart 3600C in F

7(12)

Comp/Latch

1.0 mA

Ipk(max) VClampRS

Where: 0 VClamp 1.0 VVClamp 1.67

R2R1 1

+ 0.33x103 R1R2R1 R2

UC3842B, 43B UC2842B, 43B


Figure 24. Adjustable Buffered Reduction of Clamp Level with SoftStart

Figure 25. Current Sensing Power MOSFET

Figure 26. Current Waveform Spike Suppression Figure 27. MOSFET Parasitic Oscillations

+

+

S

R

+

R

R

R2R

VClamp 1.67

R2R1 1

Ipk(max) VClampRS

5.0V Ref

Q

Bias

Osc

EA1.0V

5(9)

7(11)

6(10)

5(8)

3(5) RS

Q1

VCC Vin

1(1)

2(3)

4(7)

8(14)

R1

VClamp

R2

Where: 0 VClamp 1.0 V

C MPSA63

tSoft-Start In1 VC3 VClamp C R1 R2R1 R2

+

5.0V Ref

+

S

RQ

(11)

(10)

(8)Comp/Latch

(5) RS1/4 W

VCC Vin

KM

D SENSEFET

GS

Power Ground:To Input Source

Return

Control Circuitry Ground:To Pin (9)

Virtually lossless current sensing can be achieved with the implementation of aSENSEFET power switch. For proper operation during overcurrent conditions, areduction of the Ipk(max) clamp level must be implemented. Refer to Figures 22 and 24.

VPin 5 RS Ipk rDS(on)rDM(on) RS

If: SENSEFET = MTP10N10MRS = 200

Then : VPin 5 0.075 Ipk

7(12)

1.0 mA

Comp/Latch

(12)

+

5.0V Ref

+

S

RQ

7(11)

6(10)

5(8)

3(5)

RS

Q1

VCC Vin

S

R

5.0V Ref

Q

7(11)

6(10)

5(8)

3(5) RS

Q1

VCC Vin

C

R

The addition of the RC filter will eliminate instability caused by the leadingedge spike on the current waveform.

Series gate resistor Rg will damp any high frequency parasitic oscillationscaused by the MOSFET input capacitance and any series wiring inductance inthe gatesource circuit.

7(12) 7(12)

Rg

Comp/Latch Comp/Latch

+

+

UC3842B, 43B UC2842B, 43B


Figure 28. Bipolar Transistor Drive Figure 29. Isolated MOSFET Drive

Figure 30. Latched Shutdown Figure 31. Error Amplifier Compensation

6(10)

5(8)

3(5) RS

Q1

Vin

C1

Base ChargeRemoval

The totem pole output can furnish negative base current for enhanced transistorturnoff, with the addition of capacitor C1.

S

R

5.0V Ref

Q

7(11)

6(10)5(8)

3(5)

RS

Q1

VCCIB

+

0

Vin

IsolationBoundary

VGS Waveforms

+

0

+

0

50% DC 25% DC

IpkV(Pin1) 1.4

3 RS

NSNp

Comp/Latch

7(12)

R

C NS NP

+

+

Bias

+

Osc

R

R

R

2R

EA

5(9)

1(1)

2(3)

4(7)

8(14)

The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two transistor circuit canbe used in place of the SCR as shown. All resistors are 10 k.

MCR101

2N3905

2N3903

+

R

2R1.0mA

EA

2(3)

5(9)

2.5V

1(1)

RfCfRd

Ri

From VO

Error Amp compensation circuit for stabilizing any current mode topology except for boost and flybackconverters operating with continuous inductor current.

Rf 8.8 k

+

R

2R1.0mA

EA

2(3)

5(9)

2.5V

1(1)

RfCfRd

Rp

From VO

Error Amp compensation circuit for stabilizing current mode boost and flybacktopologies operating with continuous inductor current.

Cp

Ri

1.0 mA

+

+

5.0V Ref36V

S

RQ

Bias

+1.0mA

Osc

R

R

R

2R

EA 1.0V

7(12)

7(11)

6(10)

5(8)

3(5) RS

VCC Vin

1(1)

2(3)

4(7)

8(14)RT

CT

The buffered oscillator ramp can be resistively summed with either the voltagefeedback or current sense inputs to provide slope compensation.

Figure 32. Slope Compensation

m 3.0m

m

RfCf

Ri

Rd

From VO RSlope

MPS3904

Figure 33. 27 W OffLine Flyback Regulator

5(9)

Comp/Latch

MUR110+

+

S

R

+

R

R

5.0V Ref

Q

Bias

EA

5(9)

7(11)

6(10)

5(8)

3(5) 0.5

MTP4N50

1(1)

2(3)

4(7)

8(14)10k

4700pF

470pF

150k100pF

18k

4.7k

0.01

100

+

1.0k

115 Vac

4.7MDA202

250

56k

4.7k 3300pF

1N4935 1N4935

+ +6847

1N4937

1N4937

680pF

2.7k

L3

L2

L1

+ +

+ +

+ +

1000

1000

2200

10

10

10005.0V/4.0A

5.0V RTN

12V/0.3A

12V RTN

12V/0.3A

Primary: 45 Turns #26 AWGSecondary 12 V: 9 Turns #30 AWG (2 Strands) BifiliarWoundSecondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar WoundSecondary Feedback: 10 Turns #30 AWG (2 strands)

Bifiliar WoundCore: Ferroxcube EC353C8Bobbin: Ferroxcube EC35PCB1Gap: 0.10 for a primary inductance of 1.0 mH

MUR110

MBR1635T1

22Osc

T1

7(12)

Comp/Latch

L1L2, L3

15 H at 5.0 A, Coilcraft Z7156 25 H at 5.0 A, Coilcraft Z7157

1N5819

UC3842B, 43B UC2842B, 43B


Test Conditions ResultsLine Regulation: 5.0 V

12VVin = 95 to 130 Vac = 50 mV or 0.5%

= 24 mV or 0.1%

Load Regulation: 5.0 V

12V

Vin = 115 Vac, Iout = 1.0 A to 4.0 A

Vin = 115 Vac, Iout = 100 mA to 300 mA

= 300 mV or 3.0%

= 60 mV or 0.25%

Output Ripple: 5.0 V12V

Vin = 115 Vac 40 mVpp80 mVpp

Efficiency Vin = 115 Vac 70%All outputs are at nominal load currents, unless otherwise noted

UC3842B, 43B UC2842B, 43B


OUTLINE DIMENSIONS

N SUFFIXPLASTIC PACKAGE

CASE 62605ISSUE K

D1 SUFFIXPLASTIC PACKAGE

CASE 75106(SO8)

ISSUE T

NOTES:1. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.2. PACKAGE CONTOUR OPTIONAL (ROUND OR

SQUARE CORNERS).3. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

1 4

58

F

NOTE 2 A

B

TSEATINGPLANE

H

J

GD K

N

C

L

M

MAM0.13 (0.005) B MT

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 9.40 10.16 0.370 0.400B 6.10 6.60 0.240 0.260C 3.94 4.45 0.155 0.175D 0.38 0.51 0.015 0.020F 1.02 1.78 0.040 0.070G 2.54 BSC 0.100 BSCH 0.76 1.27 0.030 0.050J 0.20 0.30 0.008 0.012K 2.92 3.43 0.115 0.135L 7.62 BSC 0.300 BSCM 10 10 N 0.76 1.01 0.030 0.040

SEATINGPLANE

14

58

A0.25 M C B S S

0.25 M B M

h

C

X 45

L

DIM MIN MAXMILLIMETERS

A 1.35 1.75A1 0.10 0.25B 0.35 0.49C 0.19 0.25D 4.80 5.00E

1.27 BSCe3.80 4.00

H 5.80 6.20h

0 7 L 0.40 1.25

0.25 0.50

NOTES:1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.2. DIMENSIONS ARE IN MILLIMETER.3. DIMENSION D AND E DO NOT INCLUDE MOLD

PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 TOTAL IN EXCESSOF THE B DIMENSION AT MAXIMUM MATERIALCONDITION.

D

E H

A

B e

BA1

C A

0.10

UC3842B, 43B UC2842B, 43B


OUTLINE DIMENSIONS

D SUFFIXPLASTIC PACKAGE

CASE 751A03(SO14)ISSUE F

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

A

B

G

P 7 PL

14 8

71M0.25 (0.010) B M

SBM0.25 (0.010) A ST

T

FR X 45

SEATINGPLANE

D 14 PL K

C

JM

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 8.55 8.75 0.337 0.344B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7 P 5.80 6.20 0.228 0.244R 0.25 0.50 0.010 0.019

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicalsmust be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injuryor death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorolaand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorolawas negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.

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UC3842B