משובצות- הרצאה 6 | Built-In Self Test

7/30/2019 6 - | Built-In Self Test

1/120

1

Embedded Systems DesignBuilt-In Self Test (BIST)

83-651


2/120

2

General Introduction Previously we have discussed algorithmic

methods for test generation and techniques fordesign for testability (DFT)

These methods are primarily used when externaltesting is employed

Built-in self-test (BIST) is a design technique inwhich parts of a circuit are used to test the circuititself

The first part of this presentation covers the basicconcepts associated with BIST

We then focus on the problem of built-ingeneration of test patterns


3/120

3

General Introduction

Various ways of partitioning a circuit forself-testing are described, as are ways ofgenerating test patterns

Test-pattern generation techniquesdiscussed include exhaustive testing,pseudorandom testing, andpseudoexhaustive testing

The latter includes the concepts ofverification and segmentation testing


4/120

4

General Introduction Generic BIST architectures are described,

including the major ways of characterizing sucharchitectures in terms of centralized versusdistributed BIST hardware and internal versusexternal BIST hardware

Next many specific BIST architectures arepresented

Finally several advanced BIST techniques arediscussed, including the identification of a

minimal number of test sessions, the control ofBIST structures, and the notion of partial-intrusion BIST designs


5/120

5

Introduction to BIST Concepts

Built-in self-testis the capability of acircuit (chip, board, or system) to test itself

BIST represents a merger of the conceptsof built-in test(BIT) and self-test, and hascome to be synonymous with these terms

The related term built-in-test equipment(BITE) refers to the hardware and/or

software incorporated into a unit to provideDFT or BIST capability


6/120


7/120

7


In on-lineBIST, testing occurs during normalfunctional operating conditions; i.e., the circuitunder test (CUT) is not placed into a test modewhere normal functional operation is locked out

Concurrent on-lineBIST is a form of testing thatoccurs simultaneously with normal functionaloperation


8/120

8

Introduction to BIST Concepts This form of testing is usually accomplished using

coding techniques or duplication and comparison These techniques were described in more detail

in previous lecture

In nonconcurrent on-lineBIST, testing iscarried out while a system is in an idle state

This is often accomplished by executingdiagnostic software routines (macrocode) ordiagnostic firmware routines (microcode)

The test process can be interrupted at any timeso that normal operation can resume


9/120


10/120

10


Off-line testing does not detect errors inreal time, i.e., when they first occur, as ispossible with many on-line concurrent BISTtechniques

Functional off-lineBIST deals with theexecution of a test based on a functionaldescription of the CUT and often employs afunctional, or high-level, fault model

Normally such a test is implemented asdiagnostic software or firmware


11/120

11


Structural off-lineBIST deals with theexecution of a test based on the structureof the CUT

An explicit structural fault model may be

used Fault coverage is based on detecting

structural faults

Usually tests are generated and responsesare compressed using some form of anLFSR (Linear Feedback Shift Register)


12/120

12


Next we present list of several types of test

structures used in BIST circuits:

BILBO - built-in logic block observer (register)

LFSR - linear feedback shift register

MISR - multiple-input signature register ORA - (generic) output response analyzer

PRPG - pseudorandom pattern generator, often referredto as a pseudorandom number generator

SISR - single-input signature register SRSG - shift-register sequence generator; also a single-

output PRPG

TPG - (generic) test-pattern generator


13/120

13


Two common TPG circuits exist

A pseudorandom pattern generator(PRPG) is a multioutput device normallyimplemented using -an LFSR

A shift register pattern generator(SRPG)is a single-output autonomous LFSR

For simplicity the student can consider a

PRPG to represent a "parallel random-pattern generator," and a SRPG to be a"serial random-pattern generator


14/120


15/120

15

Theory and Operation of LinearFeedback Shift Registers

Here we present some of the formal propertiesassociated with linear feedback shift registers

These devices, as well as modified versions ofLFSRs, are used extensively in two capacities in

DFT and BIST designs One application is as a source of pseudorandom

binary test sequences

The other is as a means to carry out responsecompression - known as signature analysis


16/120


17/120

17


O


18/120

18


Th d O i f Li


19/120

19


For example, a binary counter consisting of nflip-flopswould go through the states 0, 1, ... , 2n-1, 0, 1, ....

The maximum number of states for such a device is 2n

The shift register shown in Figure (a) cycles through

only two states If the initial state were 00 or 11, it would never change

state

An n-bitshift register cycles through at most nstates

Notice that the output sequence generated by such adevice is also cyclic

Th d O ti f Li


20/120

20


The circuit of figure (b) starting in the initial state 111 (or000) produces a cyclic sequence of states of length 1

In figure (c) we show the sequence generated for thecircuit of figure (b) if the initial state is 011

(The student should analyze the case if the initial state is101)

In Figure (d) we illustrate the case where the statesequence generated by the feedback shift register is oflength 23 - 1

Note that for the class of circuits being illustrated, the all-0state leads to a state sequence of length 1, namely theall-0 state itself


21/120

Th d O ti f Li


22/120

22


A linear circuitis a logic network constructed from thefollowing basic components: unit delays or Dflip-flops

modulo-2 adders

modulo-2 scalar multipliers

In the analysis of such circuits, all operations are donemodulo 2

The truth table for modulo-2 addition and subtraction isshown below

Thus x+ x=- x- x=x- x= 0


23/120

Theory and Operation of Linear


24/120

24




25/120

25




26/120

26


Here ci is a binary constant, and ci= 1 implies

that a connection exists, while ci= 0 implies thatno connection exists

When ci= 0 the corresponding XOR gate can bereplaced by a direct connection from its input toits output


27/120

27

Characteristic Polynomials

A sequence of numbers a0, a1, a2, ... , am, ... can beassociated with a polynomial, called a generatingfunctionG(x), by the rule:

G(x) = a0+ a1x + a2x2+ ... + amx

m....

Let { am} =a0, a1, a2, represent the outputsequence generated by an LFSR, where ai = 0 or 1

Then this sequence can be expressed as

Recall that polynomials can be multiplied and divided(modulo 2)

m

m

mxaxG

=

=0

)(


28/120



29/120

29


From the structure of the type 1 LFSR it is seenthat if the current state (CS) of Q

i

is am-i

,for i= 1, 2, ... , n, then

Thus the operation of the circuit can be defined bya recurrence relation

Let the initial state (IS) of the LFSR bea

-1

, a-2

, ... , a-n+1

, a-n The operation of the circuit starts nclock periods

before generating the output a0

im

n

i

im aca ==

1


30/120



31/120

31


Or

Thus G(x) is a function of the initial statea-1, a-2, ... , a-nof the LFSR and the feedback

coefficients c1, c2, ... , cn The denominator in the equation above, denoted

by

is referred to as the characteristic polynomialofthe sequence {am} and of the LFSR


32/120



33/120

33


And sand since the sequence { am} is cyclic withperiod p, last equation can be rewritten as

Thus it is seen that P(x) evenly divides into 1 - xp


34/120


35/120



36/120

36

C a acte st c o y o a s For the circuit of Figure (b) (slide 17), P(x) = 1+ x+ x2+

x3, and for Figure (d) (slide 18), P(x) = 1 + x2+ x3



37/120

37

y

Referring to the shift operator (slide 34), let

y-k

ai(t) = ai(t-k) Then, carrying out the same algebraic manipulation as

before, we obtain

or equivalently

Again the term in the brackets can be considered to bea characteristic polynomial of the LFSR



38/120

38

y Replacing yby xwe obtain

P*(x) is said to be the reciprocal polynomialof P(x),since P*(x) = xnP(1/x)

Thus every LFSR can be associated with two

characteristic polynomials


39/120



40/120

40

y

If in figure of type 1 LFSR (slide 24) one associates

xi

with Qithen p(x) can be read off directly from thefigure

If, however, one associates xiwith Qn-iand labelsthe input to the first flip-flop Q

0

, then P*(x) can beread off directly from the figure

Figure in next slide illustrates these two labelings

Finally, note that a given characteristic polynomial,

say Q(x), can be realized by two different LFSRsdepending on the labeling used


41/120



42/120

42

y

Referring to figure of type 2 LFSR (SLIDE 25), we seethat for i = 2, 3, ... , n

Ifwe define am(t) =0, then the equation is also true for

i =1 Let xbe a "shift" operator such that xkai(t) = ai(t-k)

Then the equations can be written as

for i = 1, 2, ... , n



43/120

43

Multiplying the i-th equation by x-i+1we get

Summing these nequations and canceling terms that

appear on both sides of the equation yield



44/120

44

Or

Multiplying by xnwe get

The term in the brackets is the characteristicpolynomial for the type 2 LFSR

Again it can be shown that a characteristic

polynomial P(x) has two type 2 realizations, orconversely, a type 2 LFSR can be associated withtwo characteristic polynomials that are reciprocalsof each other

Periodicity of LFSRs


45/120

45

y

We have seen that an LFSR goes through a cyclic

or periodic sequence of states and that the outputproduced is also periodic

The maximum length of this period is 2n- 1, wherenis the number of stages

Here we consider properties related to the periodof an LFSR

Most results will be presented without proof



46/120

46

Theorem: If the initial state of an LFSR is

a-1 = a-2 =... = a1-n =0, and a-n= 1, then the LFSRsequence {am} is periodic with a period that is thesmallest integer kfor which P(x) divides (1-xk)

Definition: If the sequence generated by an n-stage

LFSR has period 2n- 1, then it is called a maximum-length sequence

Definition: The characteristic polynomial associatedwith a maximum-length sequence is called a primitive

polynomial



47/120

47

Definition: An irreducible polynomialis one thatcannot be factored; i.e., it is not divisible by any otherpolynomial other than 1 and itself

Theorem : An irreducible polynomial P(x) of degree nsatisfies the following two conditions:

For n 2, P(x) has an odd number of terms including the 1term

For n 4, P(x) must divide (evenly) into 1 + xk, where

k= 2n- 1

The next result follows from previous theorems



48/120

48

Theorem: An irreducible polynomial is primitive if thesmallest positive integer kthat allows the polynomial todivide evenly into 1 + xkoccurs for k= 2n- 1, where nisthe degree of the polynomial

The number of primitive polynomials for an n-stage

LFSR is given by the formula

Where

and pis taken over all primes that divide n



49/120

49

Next table shows some values of

Figure in next slide gives one primitive polynomial forevery value of nbetween 1 and 36

A shorthand notation is employed


50/120

Characteristics of Maximum-LengthS


51/120

51

Sequences

Sequences generated by LFSRs that are associatedwith a primitive polynomial are called pseudorandomsequences, since they have many properties like thoseof random sequences

However, since they are periodic and deterministic, theyare pseudorandom, not random

Some of these properties are listed next



52/120

52

Sequences

In the following, any string of 2

n

- 1 consecutive outputsis referred to as an m-sequence

Property1. The number of 1s in an m-sequence differsfrom the number of 0s by one

Property2. An m-sequence produces an equal numberof runs of 1s and 0s.



53/120

53

Sequences

Property3. In every m-sequence, one half the runshave length 1, one fourth have length 2, one eighth havelength 3, and so forth, as long as the fractions result inintegral numbers of runs

These properties of randomness make feasible the useof LFSRs as test sequence generators in BIST circuitry

Now we will return back to BIST

Hardcore


54/120

54

Some parts of a circuit must be operational to

execute a self-test This circuitry is referred to as the hardcore

At a minimum the hardcore usually includes power,

ground, and clock distribution circuitry The hardcore is usually difficult to test explicitly

If faulty, the self-test normally fails

Thus detection is often easy to achieve, but little ifany diagnostic capability exists

Hardcore


55/120

55

If a circuit fails during self-test, the problem may be

in the hardcore rather than in the hardwarepresumably being tested

The hardcore is normally tested by external testequipment or is designed to be self-testable byusing various forms of redundancy, such asduplication or self-checking checkers (as wediscussed in previous lectures)

Normally a designer attempts to minimize thecomplexity of the hardcore

Levels of Test Production Testing


56/120

56

We refer to the testing of newly manufactured

components as production testing Production testing can occur at many levels, such

as the chip, board, or system levels

Using BIST at these levels reduces the need forexpensive ATE in go/no-go testing and simplifiessome aspects of diagnostic testing



57/120

57

For example, the Intel 80386 microprocessor

employs about 1.8 percent area overhead for BISTto test portions of the circuit that would be difficultto test by other means

The BIST aspects of several other chips and/orboards are discussed in the literature



58/120

58

When implemented at the chip level along with

boundary scan, BIST can be used effectively at alllevels of a system's hierarchy

Since many BIST techniques can be run in realtime, this method is superior to many non-BISTapproaches and to some extent can be used fordelay testing

It is not applicable, however, to parametric testing

Levels of Test Field Testing


59/120

59

BIST can be used for field-level testing, eliminating

the need for expensive special test equipment todiagnose faults down to field-replaceable units

This can have a great influence on the

maintainability and thus life-cycle costs of bothcommercial and military hardware

For example, the U.S. military is attempting toimplement the concept of two-level maintenance

Levels of Test Field Testing


60/120

60

Here a system must carry out a self-test and

automatically diagnose a fault to a field-replaceable unit, such as a printed circuit board

This board is then replaced "in the field" and the

faulty board is either discarded or sent to a depotfor further testing and repair

Test-Pattern Generation for BIST


61/120

61

Here, various TPG designs will be described

We assume that the unit being tested is an n-input,m-outputcombinational circuit

The various forms of testing and related TPGs are

summarized next

Test-Pattern Generation for BIST


62/120

62

Exhaustive testing

Exhaustive test-pattern generators Pseudorandom testing

Weighted test generator

Adaptive test generator

Pseudoexhaustive testing Syndrome driver counter

Constant-weight counter

Combined LFSR and shift register

Combined LFSR and XOR gates Condensed LFSR

Cyclic LFSR


63/120


64/120

Pseudorandom Testing


65/120

65

Pseudorandom testingdeals with testing a circuit

with test patterns that have many characteristics ofrandom patterns but where the patterns aregenerated deterministically and hence are

repeatable Pseudorandom patterns can be generated with or

without replacement



66/120

66

Generation with replacement implies that a test

pattern may be generated more than once; withoutreplacement implies that each pattern is unique

Not all 2ntest patterns need be generated

Pseudorandom test patterns without replacementcan be generated by an autonomous LFSR

Pseudorandom testing is applicable to both

combinational and sequential circuits



67/120

67

Fault coverage can be determined by fault

simulation

The test length is selected to achieve anacceptable level of fault coverage

Unfortunately, some circuits contain random-pattern-resistant faults and thus require longtest lengths to insure a high fault coverage


68/120

Pseudorandom TestingConsider for example a 4 input AND gate


69/120

69

Consider, for example, a 4-input AND gate

When applying unbiased random inputs, the probabilityof applying at least one 0 to any input is 15/16

A 0 on any input makes it impossible to test any otherinput for s-a-0or s-a-1

Thus there is a need to be able to generate test patternshaving different distributions of 0s and 1s

Some results relating the effectiveness of testing interms of test length and fault coverage to the distribution

characteristics of the test patterns have been reported inthe literature

Weighted Test Generation


70/120

70

A weighted test generatoris a TPG where the

distribution of 0s and 1s produced on the outputlines is not necessarily uniform

Such a generator can be constructed using an

autonomous LFSR and a combinational circuit For example, the probability distribution of 0.5 for a

1 that is normally produced by a maximal-lengthLFSR can be easily changed to 0.25 or 0.75 toimprove fault coverage

Weighted Test Generation


71/120

71

When testing a circuit using a weighted test

generator, a preprocessing procedure is employedto determine one or more sets of weights

Different parts of a circuit may be tested more

effectively than other parts by pseudorandompatterns having different distributions

Once these weights are determined, theappropriate circuitry can be designed to generatethe pseudorandom patterns having the desireddistributions


72/120

Pseudoexhaustive Testing


73/120

73

Pseudoexhaustivetesting achieves many of the

benefits of exhaustive testing but usually requiresfar fewer test patterns.

It relies on various forms of circuit segmentation

and attempts to test each segment exhaustively Because of the many subjects that are associated

with pseudoexhaustive testing, we will first brieflyoutline the main topics to be discussed in this

section



74/120

74

A segment is a subcircuit of a circuit C

Segments need not be disjoint

There are several forms of segmentation, afew of which are listed below

1. Logical segmentation

a. Cone segmentation (verification testing)

b. Sensitized path segmentation

2. Physical segmentation



75/120

75

When employing a pseudoexhaustive test to an

n-inputcircuit, it is often possible to reconfigurethe input lines so that tests need only begenerated on mlines, where m< n, and these m

lines can fanout and drive the nlines to the CUT These msignals are referred to as test signals

A procedure for identifying these test signals will

be presented



76/120

76

Pseudoexhaustive testing can often be

accomplished using constant-weight testpatterns

Some theoretical results about such patterns

will be presented We will also describe several circuit

structures that generate these patterns as

well as other patterns used inpseudoexhaustive testing

Logical Segmentation - Conesegmentation


77/120

77

In cone segmentationan moutput circuit is

logically segmented into mcones, each coneconsisting of all logic associated with one output

Each cone is tested exhaustively, and all cones

are tested concurrently This form of testing was originally suggested by

McCluskey [1984] and is called verification

testing


78/120


79/120

Logical Segmentation Sensitized-Path Segmentation


80/120

80

Some circuits can be segmented based on the

concept of path sensitization A trivial example is shown in next figure

Logical Segmentation Sensitized-Path Segmentation


81/120

81

g

To test C1

exhaustively, patterns are appliedto A while Bis set to some value so that D= 1

Thus a sensitized path is established from Cto F

C2 is tested in a similar manner

By this process, the AND gate is also completelytested

Thus this circuit can be effectively tested usingonly test patterns, rather than

1

2

n

122 21 ++nn 212

nn +

Constant-Weight Patterns


82/120

82

Consider two positive integers nand k, where

k n Let Tbe a set of binary n-tuples

Then Tis said to exhaustively cover allk-subspacesif for all subsets of kbit positions,each of the 2kbinary patterns appears at leastonce among the Tn-tuples

For example, the set Tshown in next slide,

exhaustively covers all 2-spaces (all possible 2 1sin 3 bit tuples)



83/120

83

If ITlmin is the smallest possible size for such a setT, then clearly 2k ITl

min 2n

A binary n-tupleis said to be of weight kif itcontains exactly k1s

There are binary n-tupleshaving weight k

The following results will be presented herewithout proof

k

n


84/120

Constant-Weight Patterns Example 1: n= 20, k= 2, n- k+ 1 = 19


85/120

85

p , ,

Case1: c=0

Setting w= 0 mod 19 produces w= 0 and 19

Thus T0consists of the all-0 patterns and 20patterns of weight 19

Hence and

Constant-Weight Patterns Case2: c=1


86/120

86

Setting w= 1 mod 19 results in w= 1, 20

Therefore

and

Constant-Weight Patterns Case3: 2c 18


87/120

87

For 2c 18, w= cmod 19 implies that w= c

Thus in each case Tcconsists of all weight-c

binary n-tuples, and ITcI =

Note that T0and T1 are the smallest among the 19 sets; in fact T1 and T0are complements of

each other

c

n

Constant-Weight Patterns Example 2: n= 20, k= 3, n- k+ 1 = 18


88/120

88

p

Case1: c=0

For w= 0 mod 18, w= 0 and 18

Thus

Case2: c = 1 For w=1 mod 18, w=1, 19 and

Constant-Weight Patterns Case3: c = 2


89/120

89

For w= 2 mod 18, w =2, 20 and T2 is thecomplement of T0

Case4: 3 c 17

For w= cmod 18, 3 c 17, we have w= c

Note that for both examples, for any value of w,0 w 20, all n-tuplesof weight wexist in exactlyone case considered

The general situation is covered by the followingcorollary

Constant-Weight Patterns Corollary 1: There are (n - k+1) solution sets Ti ,


90/120

90

0 i n- kobtained from Theorem 1, and these

solution sets are disjoint and partition the set of all2nn-tuplesinto disjoint classes

Since these are (n - k+1) solution sets thatpartition the set of 2ndistinct n-tuplesinto (n - k+1)disjoint sets, and the smallest set cannot be largerthan the average set, then an upper bound on thesize of ITlmin is

Constant-Weight Patterns Theorem 2: Let Tcbe a set generated according


91/120

91

to Theorem 1

Then Tcis minimal; i.e., no proper subset of Tcalso exhaustively covers all k-subspaces, if c kor c= n- k

Example 3: n=6, k=2, n- k+ 1 =5 For c= 3, w= 3 mod 5, thus w= 3and

One subset of T3that exhaustively covers all 2-subspaces is shown in next slide as T'3



92/120

92

T'3is minimal and IT'3I = 6

The upper bound of ITminI Bnis tight when kisclose to nand is loose when kis small

Bngrows exponentially as nincreases,

independent of the value of k


93/120

Constant-Weight Patterns Case2: n= k+ 1


94/120

94

For this case w= cmod 2, and T0consists of theset of all binary n-tuples having odd parity

and T1 consists of the set of all n-tuples havingeven parity

This situation is shown below for the case of n= 4and k= 3


95/120


96/120


97/120


98/120


99/120

Identification of Test SignalInputs

Next figure shows a non-MTC circuit


100/120

100

e t gu e s o s a o C c cu t

Here every output is a function of only two inputs,but three test signals are required

However, each output can still be testedexhaustively by just four test patterns


101/120


Each output is a function of only two inputs, but


102/120

102

Each output is a function of only two inputs, but

five test patterns are required to exhaustively testall six outputs

We next present a procedure for partitioning theinputs of a circuit to determine (1) the minimalnumber of signals required to test a circuit and (2)which inputs to the CUT can share the same testsignal

We will also show how constant-weight patternscan be used to test the circuit

Identification of Test SignalInputs The various steps of the procedure will be illustrated as


103/120

103

p p

they are presented using the circuit C* shown infunctional form in next figure

From these results it will be possible to identify MTCcircuits and to construct tests for MTC and non-MTCcircuits

Identification of Test SignalInputs Procedure 1: Identification of Minimal Set of Test


104/120

104

Signals Step1: Partition the circuit into disjoint subcircuits

C * consists of only one partition

Step2: For each disjoint subcircuit, carry out the

following stepsa. Generate a dependency matrix

b. Partition the matrix into groups of inputs so that two or more

inputs in a group do not affect the same output

c. Collapse each group to form an equivalent input, called a testsignal input

Identification of Test SignalInputs For an n-input, m-outputcircuit, the dependency


105/120

105

p p y

matrixD =[dij]consists of mrows and ncolumns,where dij=1 if output idepends on input j; otherwisedij= 0

For circuit C *, we have

Identification of Test SignalInputs Reordering and grouping the inputs produce the


106/120

106

modified matrix Dg

In each group there must be less than two 1s in eachrow and the number of groups should be minimal

This insures that no output is driven by more than oneinput from each group

Identification of Test SignalInputs Procedures for finding such a partition, which is a NP-


107/120

107

complete problem, can be found in the literature The collapsed equivalent matrix Dc is obtained by

ORing each row within a group to form a singlecolumn

The result for circuit C* is


108/120

Identification of Test SignalInputs For Dc, we have p= 4 and w= 3


109/120

109

A universal minimal pseudoexhaustive test sethaving parameters (p,w) is a minimal set of test patterns

that contains, for all subsets consisting

of wof the psignal lines, all 2wtest patterns

The properties of these test sets are determined by therelative values of pand w, where by definition, p w

For a specific circuit, if all outputs are a function of winputs, then this test set is minimal in length

w

p

Identification of Test SignalInputs Otherwise it may not be


110/120

110

Step4: Construct the test patterns for the circuitbased upon the following three cases:

Case1: p= w

Case2: p= w+ 1

Case3: p> w+ 1

Identification of Test SignalInputs Case1: p= w


111/120

111

This case corresponds to MTC circuits and the testconsists of all 2ptest patterns of pbits

The test can be easily generated by a counter or acomplete LFSR

Clearly this is a universal minimal pseudoexhaustivetest set

This case applies to Figure in slide 98, where p= w= 2

Referring to the prior discussion on constant weightpatterns, this case corresponds to the previous casewhere k= nresulting in the test set T0


112/120



113/120

113

Note that for any subset of three columns, all 23 binarytriplets occur

This pseudoexhaustive test set consists of 8 patterns,while an exhaustive test would consist of 128 patterns

Identification of Test SignalInputs Each column represents an input to each line in a


114/120

114

group; e.g., column A can be the input to lines aand cin the circuit shown in figure in slide 108

This case also applies to the circuit shown in figure inslide 100, where p= 3 and test patterns of even parity

are selected Case3: p> w+ 1

For this case, the test set consists of two or more

pattern subsets, each of which contains all possiblepatterns of pbits having a specific constant weight

Identification of Test SignalInputs The total number of test patterns Tis a function of pand w

Next figure shows the value of the constant weights and T for


115/120

115

Next figure shows the value of the constant weights and Tforvarious values of pand w

Identification of Test SignalInputs Unfortunately, constant weights do not exist for all pairs of

p and w


116/120

116

pand w

For such cases, wcan be increased so as to achieve aconstant-weight pseudoexhaustive test, but it may not be

minimal in length

The minimal test set for p= 5 and w= 3 corresponding tothe constant-weight pair (1,4) (see figure in previousslide) is shown in next figure

Identification of Test SignalInputs Unfortunately it is not always easy to construct a circuit to

generate a pseudoexhaustive test set for p > w + 1 and the


117/120

117

generate a pseudoexhaustive test set for p> w+ 1, and the

hardware overhead of some of these circuits is sometimesquite high

In the next subsection several techniques for designingcircuits that generate pseudoexhaustive tests will be briefly

described Many of these designs do not generate minimal test sets, but

the techniques lead to efficient hardware designs

Because most TPGs use some form of an LFSR, and since

more than one test sequence is sometimes needed, oftenmore than one seed value is required for initializing the stateof the LFSR

Test-Pattern enerators forPseudoexhaustive Tests Syndrome-Driver Counter


118/120

118

For the circuit shown in figure in slide 79, y1 = f1(x1,x3),y2= f2(x1,x2), y3= f3(x2,x3), and y4= f4(x3,x4)

Thus no output is a function of both x1 and x4, or of x2and x4 (The width of this circuit is 3)

Hence x1 and x4 (or x2 and x4) can share the sameinput during testing

Thus this circuit can be pseudoexhaustively tested by

applying all 23

input to x1, x2, and x3, and by havingthe line driving x1 or x2 also drive x4


119/120

Syndrome-Driver Counter In general the test patterns consisting of all 0s and all 1s

are not required; hence 2p- 2 tests can be used


120/120

120

are not required; hence 2p- 2 tests can be used

The major problem with this approach is that when pisclose in value to na large number of test patterns arestill required

This testing scheme was proposed by Barzilai et al. anduses a syndrome-driver counter(SDC) to generatetest patterns

The SDC can be either a binary counter or an LFSR

and contains only pstorage cells

Documents

משובצות- הרצאה 6 | Built-In Self Test