µ…è°ˆ FPGA ç„ç”µè·¯è®¾è® ¥‘T爱¹³ 2005/11/13

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浅谈基于 FPGA 的电路设计 报告人:吴爱平 2005/11/13. 参考资料. VHDL 电路设计技术 国防工业出版社 CPLD 系统设计技术入门与应用 电子工业出版社 基于 FPGA 的嵌入式系统设计 西电出版 Altera FPGA/CPLD 设计(基础篇) EDA 先锋工作室 网站: WWW.PLD.COM.CN WWW.EDACN.NET WWW.ALTERA.COM. 浅谈基于 FPGA 的电路设计. FPGA 概述 设计过程 注意事项. 温馨提示. 如果你打算5年成为高手,你可能2-3年就可以达到; - PowerPoint PPT Presentation

Text of µ…è°ˆ FPGA...

  • FPGA2005/11/13

  • VHDL CPLD FPGA Altera FPGA/CPLD() EDA WWW.PLD.COM.CN WWW.EDACN.NET WWW.ALTERA.COM

  • FPGAFPGA

  • 52-315

    ---

  • FPGA

  • 708090PROM PLA PLA GALFPGAEPLD CPLDSoPC2000

  • PLD FPGAField Programmable Gates Array CPLD Complex Programmable Logic Device

  • AlteraXilinxLattice

  • PLD/FPGA2005

  • ALTERA

    FLEX10 K LC84 TC144 BC356 FLEX10KA TC100 BC356 ACEX1K 1K10 1K30 1K50 MAX7000 EPM7128 MAX II EPM240 570 1270 Cyclone EP1C3 4 6 12 20 Stratix EP1S10 20 25 30 CycloneII EP2C5 8 20 35 50 70 Stratix II EP2S15 30 60 90 130

  • XiLinx

    XC3000 XC4000 XC9500 XC9536XC9572XC95144 XC9500XL XC9536XL,72XL Spartan 3/3L XC3S50,200,400 Virtex II XC2V40,80,250Spartan 3E XC3S100E,250E Virtex-4 LX 4VLX15,25,40,60 SX 4VSX25,35,55 FX 4VFX12

  • Latticeisp1000/2000/5000/8000 ispLSI1016,1024,1032,1048ispMACH4000 V/B/Z ispMACH4032V,64V,128V,256V ispMACH4032B,64B,128B,256B ispMACH4032Z,64Z,128Z,256Z Lattice EC/ECP EC1,EC3,EC6/ECP6,EC15/ECP15

  • ALTERA (Cytech) (Arrow)(Achieva)(Future)(Wintech)XiLinx InsightAVNET Lattice

  • PLD

    _1092499859.vsd

  • (Product-Term)(Look-Up-Table)

  • CPLD/FPGATpdPOR

  • Altera MAX PLUS II QUARTUS II Xilinx Foundation ISE Lattice ispLEVER ispDesignEXPERNT

  • ModleSimActive HDLSynplify/ Synplify ProDebussyIP CoreSOPC BuilderDSP Builder

  • ABELAHDLVerilog VHDLsystemCHandle-C

  • ABEL ABELPLDABEL-HDL GAL LatticeispEXPERT,XilinxFOUNDATIONWEBPACKEDAABEL-HDL

  • AHDL ALTERAHDL,AHDL ALTERA

  • Verilog Verilog HDLC1990CADENCEVerilog HDL,LVIVerilog HDLIEEEIEEE Standard 1364-1995 1 2 3IC90% 4EDA

  • VHDL Very-High-Speed Integrated Circuit HardwareDescription Language 19821987VHDLIEEE IEEE-1076IEEE1076-1993 1 2EDA 3VHDL

  • ()

  • STEP1 STEP2VHDLSTEP3 STEP4ProjectSTEP5 STEP11 STEP9STEP8 STEP7STEP6STEP10 /VHDL

  • Step1 My_prjct

  • Step2 VHDL

  • Step3 VHDL mux21a.vhd

  • Step4

  • ACEX1KEP1K30Step5

  • Step6

  • VHDLVHDL1993

  • Step7

  • SNFLIST

  • SNFOK

  • OptionsSnap to Grid()

  • END TIME65

  • 1bb800ns

  • a2us

  • Step8

  • mux21a

  • Step9

  • ADD

  • Step10 /

  • FPGAFPGA

  • latchRTL

  • BCDA

  • VCCINT VCCIOPin to pin I/O

  • EPF 10K10 TQFP C070 84 -1EPM 7128 PQFP I -4585 144 -2EPC 12 CQFP M-55125 208 -3EP1C 34 BGA 240 -4EP1S 1020 PLCC 356EP2C 58 PDIPEP2S 1530

    www.altera.com

  • I/O

  • PLLDSPRAM FLASH