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차세대 SoC (System on Chip) 의 요구사항. Darwin’s Philosophy on Wireless Communications?. Soft eye?. 프로젝터 폰. Down Sizing 추세. What is System on Chip?. Display Driver IC (DDI): STN - TFT - OLED. Camera Chipset: CIS - CCD - ISP. Connectivity: Wireless LAN - GPS - Bluetooth. SoC. - PowerPoint PPT Presentation
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SKKU 휴대폰학과 © 조준동 2008 1
조 준 동
2008.1
차세대 SoC (System on Chip) 의 요구사항
SKKU 휴대폰학과 © 조준동 2008 2
Darwin’s Philosophy on Wireless Communications?
SKKU 휴대폰학과 © 조준동 2008 3
Soft eye?
SKKU 휴대폰학과 © 조준동 2008 4
프로젝터 폰
SKKU 휴대폰학과 © 조준동 2008 5
Down Sizing 추세
SKKU 휴대폰학과 © 조준동 2008 6
Processor: AP - MC
Modem: GSM/GPRS - WCDMA - CDMA2000
Connectivity: Wireless LAN - GPS - Bluetooth
RF/Analog: Rx - Tx - Zero IF - PM
Camera Chipset: CIS - CCD - ISP
Display Driver IC (DDI): STN - TFT - OLED
Smart Card: Smart Card: SIMSIM
Flash Memory: Flash Memory: Code/Data Storage Code/Data Storage
SIP / MCPSIP / MCP
RAM: Mobile DRAM - SRAM - UtRAM
What is System on Chip? What is System on Chip?
SoCSoC
SKKU 휴대폰학과 © 조준동 2008 7
고성능 및 저전력의 필요성
3D graphics
Moore’s law
Shannon’s lawShannon’s law
((2.8x / 18m)
2G (IS-95)
9.6kbps
3G (CDMA 1xEV)
3,100kbps
4G (1GMbps~
100Mbps)
20031995 2012
Battery capacityQVGA
D1
HD (720p)
Full HD (1080i)
Mobile MultimediaMobile Multimedia
Design Complexity
Productivity Gap: Design complexity vs. Moore’s law
Power Gap: Design complexity vs. Battery
SKKU 휴대폰학과 © 조준동 2008 8
임베디드 프로세서 (ARM) 0.5 MOPS/mW
신호처리 프로세서ASIPs, DSPs
3 MOPS/mW
신호처리ASIC
가용성
에너
지 효
율(M
OP
S/m
W)
0.1
1
10
100
1000
200 MOPS/mW
10-80 MOPS/mW
6
FPFA
Flexibility-Energy Gap
FPFA : Field Programmable Function Array
Sensor network design space
Wireless embedded systems design space
SKKU 휴대폰학과 © 조준동 2008 9
Dual-Core (DSP+ARM) Platform
SKKU 휴대폰학과 © 조준동 2008 10
Cell Processor
SKKU 휴대폰학과 © 조준동 2008 11
차세대 SoC 의 생산성 증대를 위한 5 가지 요구사항
1. High Performance 2. Fast Verification3. Small Form Factor4. Low Power Solutions5. Design-Technology Integration for
Manufacturability
SKKU 휴대폰학과 © 조준동 2008 12
1. High-Performance: CMP +NoC
Heterogeneous Heterogeneous Chip Multi-processorChip Multi-processor
ArchitectureArchitecture
P
IP
Mem
IP
PE
PE
PE
P
Mem
PE
No C
0
50
100
150
200
250
300
350
400
2004 2007 2010 2013 2016
#. PEs
Source: ITRS 2005 draft
Technology Evolution
SKKU 휴대폰학과 © 조준동 2008 13
2. Fast Verification:Embedded System Level
ComplexityComplexity
Moore’s LawMoore’s Law2x / 18m2x / 18m
Nielsen’s LawNielsen’s Law2x / 12m2x / 12mEmbedded SWEmbedded SW
2x / 10m2x / 10m
System specification
Architecture design
RTL design
UML / Java / MatLab
SystemC / ADL
Verilog / VHDL
ESL
ctrl1/cmd1/
Req
Addr
Grant
Data
ack1
ack0
TLMTLM
SKKU 휴대폰학과 © 조준동 2008 14
Time-to-Market Challenges and Trends
Cost
($M
)
$0
$500,000
$1,000,000
$1,500,000
250 180 150 130 90
Technology (nm)
Ma
sk
Co
sts
Des
ign
Cos
ts I
ncre
ased
SW
E
ffor
t
Mas
k C
osts
Shift to• Re-use Strategy at all levels• Higher Level of Abstractions• Software !!!
A. Sangiovanni-Vincentelli, DAC 04
SKKU 휴대폰학과 © 조준동 2008 15
MobileMobileAPAP
32MB32MBNANDNAND
16MB16MBSDRAMSDRAM
~35mm~35mm
~25m
~25m
mm
16MB16MBSDRAMSDRAM
17mm17mm
17
mm
17
mm
FlashSDRAM
SDRAM
Mobile AP
EMI ReductionEMI Reduction
60% Smaller Area60% Smaller Area
▷▷ 8-layers of MCP8-layers of MCP▷ ▷ Cost reduction by Cost reduction by 15%15%
3. Small Form Factor
SiP: Mobile Application Processor + Mobile MemorySiP: Mobile Application Processor + Mobile Memory
SKKU 휴대폰학과 © 조준동 2008 16
Thermal Aware Architecture Design• Architectural floorplanner• 3D Chip
SKKU 휴대폰학과 © 조준동 2008 17
• MTCMOS
• Clock Gating
• Multi-Vdd
• Tr Sizing
• VTCMOS
• Multi-Vt
• SOI
• High- Metal Gate
Device Circuit Architecture Runtime•Parallelization
•GALS
DAC 2004
4. Low Power Solutions
DVFS
1.2V, 350MHz
1.5V, 500MHz
1.0V
200MHz
Multi-Vdd
•DPM/DVS
Active
Active
Standby
Standby
VBP
VBN
VDD
VSS
VTCMOS
• MTCMOS
SKKU 휴대폰학과 © 조준동 2008 18
Low Power Techniques for HW
Should consider the power consumption during all design steps
High-Vth cell
Low-Vth cell
Leakage Power Reduction
Power Analysis / Integrity
Dynamic Power Reduction
MTCMOSMTCMOS Multi-Vth VTMOS
RTL/Vectorless Analysis IR-drop Power Mesh Electro Migration
Clock Gating Multi-Vdd DVFSDVFS
SKKU 휴대폰학과 © 조준동 2008 19
Statistical Analysis
CriticalTiming,power
Designer’sIntention
?
?
5. Design-Technology Integration for Manufacturability (DfM)
VariationInformation
NA, ToxNA, Tox
Latency, PowerLatency, Power
Fault ProbabilityFault Probability
Vdd, TempVdd, Temp
Vt, Lg, L, t, tILDVt, Lg, L, t, tILD
Quantum Physics
Mask / Process Design
Architecture Design
Logic / PhysicalDesign
Algorithm DesignFault-tolerant algorithm
Yield-improving architecture
Statistical STA
SKKU 휴대폰학과 © 조준동 2008 20
퀴 즈
1. 다음중 차세대 SoC 의 생산성 증대를 위한 5 가지 요구 사항에 포함되지 않은 것은 ? ( 답 :1)
1)DSP 2) DfM 3) Small Form Factor 4) Low Power Solutions
2. 다음 중 ESL 에서 사용하는 검증 언어가 아닌것은 ? ( 답 : 3) 1) UML 2)Java 3) RTL 4) System-C
3. 다음중 저전력 기술이 아닌 것은 ? ( 답 : 4) 1) TR-sizing 2) DPM/DVS 3) MTCMOS 4) ESL
SKKU 휴대폰학과 © 조준동 2008 21
요 약
Nano Era SoC has Endless Possibilities with
1. High Performance 2. Fast Verification3. Small Form Factor4. Low Power Solutions5. Design-Technology Integration for Manufacturability