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102-1 Under-Graduate Project: RTL Coding Style. Speaker: 黃乃珊 Adviser: Prof. An- Yeu Wu Date: 2013/12/12. Outline. Principles of RTL Coding Styles Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis Debugging Tool: nLint. - PowerPoint PPT Presentation
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ACCESS IC LAB
Graduate Institute of Electronics Engineering NTU
102-1 Under-Graduate ProjectRTL Coding Style
Speaker黃乃珊Adviser Prof An-Yeu Wu
Date 20131212
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P2
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P3
Pre-RTL Preparation Checklist Communicate design issues with your teammates
Naming conventions directory trees and other design organizations
Have a specification for your design Everyone should have a specification BEFORE they start
coding Design partition
Follow the specificationrsquos recommendations for partition Break the design into major functional blocks
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P4
RTL Coding Style Create a block level drawing of
your design before you begin coding Draw a block diagram of the functions and
sub-functions of your design
Hierarchy design
Always think of the poor guy who has to read your RTL code Easy to understand Meaningful names Comments and headers
Start Cmpt End
haha55
yaya66
Sum_2
Multiply_0
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P5
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P6
File Headers Include informational header at the top of every source
file including scripts Filename Author information eg name emailhellip Description of function and list of key features of the module Available parameters Reset scheme and clock domain Date the file was created and modified Critical timing and asynchronous interface
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P7
File Header Example DCTv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P8
Identifiers Naming Rule Begin with an alpha character (a-z A-Z) or
an underscore (_) and can contain alphanumeric dollar signs ($) and underscore Examples of illegal identifiers
34net ab_net n238
Up to 1023 characters long
Case sensitive eg sel and SEL are different identifiers
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P9
General Naming Conventions(13) Lowercase letters for all signals variables and port
names reg is used in procedural block
Uppercase letters for constants and user-defined types eg `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names Use ram_addr for RAM address bus instead of ra
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P2
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P3
Pre-RTL Preparation Checklist Communicate design issues with your teammates
Naming conventions directory trees and other design organizations
Have a specification for your design Everyone should have a specification BEFORE they start
coding Design partition
Follow the specificationrsquos recommendations for partition Break the design into major functional blocks
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P4
RTL Coding Style Create a block level drawing of
your design before you begin coding Draw a block diagram of the functions and
sub-functions of your design
Hierarchy design
Always think of the poor guy who has to read your RTL code Easy to understand Meaningful names Comments and headers
Start Cmpt End
haha55
yaya66
Sum_2
Multiply_0
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P5
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P6
File Headers Include informational header at the top of every source
file including scripts Filename Author information eg name emailhellip Description of function and list of key features of the module Available parameters Reset scheme and clock domain Date the file was created and modified Critical timing and asynchronous interface
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P7
File Header Example DCTv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P8
Identifiers Naming Rule Begin with an alpha character (a-z A-Z) or
an underscore (_) and can contain alphanumeric dollar signs ($) and underscore Examples of illegal identifiers
34net ab_net n238
Up to 1023 characters long
Case sensitive eg sel and SEL are different identifiers
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P9
General Naming Conventions(13) Lowercase letters for all signals variables and port
names reg is used in procedural block
Uppercase letters for constants and user-defined types eg `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names Use ram_addr for RAM address bus instead of ra
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P3
Pre-RTL Preparation Checklist Communicate design issues with your teammates
Naming conventions directory trees and other design organizations
Have a specification for your design Everyone should have a specification BEFORE they start
coding Design partition
Follow the specificationrsquos recommendations for partition Break the design into major functional blocks
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P4
RTL Coding Style Create a block level drawing of
your design before you begin coding Draw a block diagram of the functions and
sub-functions of your design
Hierarchy design
Always think of the poor guy who has to read your RTL code Easy to understand Meaningful names Comments and headers
Start Cmpt End
haha55
yaya66
Sum_2
Multiply_0
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P5
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P6
File Headers Include informational header at the top of every source
file including scripts Filename Author information eg name emailhellip Description of function and list of key features of the module Available parameters Reset scheme and clock domain Date the file was created and modified Critical timing and asynchronous interface
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P7
File Header Example DCTv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P8
Identifiers Naming Rule Begin with an alpha character (a-z A-Z) or
an underscore (_) and can contain alphanumeric dollar signs ($) and underscore Examples of illegal identifiers
34net ab_net n238
Up to 1023 characters long
Case sensitive eg sel and SEL are different identifiers
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P9
General Naming Conventions(13) Lowercase letters for all signals variables and port
names reg is used in procedural block
Uppercase letters for constants and user-defined types eg `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names Use ram_addr for RAM address bus instead of ra
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P4
RTL Coding Style Create a block level drawing of
your design before you begin coding Draw a block diagram of the functions and
sub-functions of your design
Hierarchy design
Always think of the poor guy who has to read your RTL code Easy to understand Meaningful names Comments and headers
Start Cmpt End
haha55
yaya66
Sum_2
Multiply_0
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P5
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P6
File Headers Include informational header at the top of every source
file including scripts Filename Author information eg name emailhellip Description of function and list of key features of the module Available parameters Reset scheme and clock domain Date the file was created and modified Critical timing and asynchronous interface
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P7
File Header Example DCTv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P8
Identifiers Naming Rule Begin with an alpha character (a-z A-Z) or
an underscore (_) and can contain alphanumeric dollar signs ($) and underscore Examples of illegal identifiers
34net ab_net n238
Up to 1023 characters long
Case sensitive eg sel and SEL are different identifiers
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P9
General Naming Conventions(13) Lowercase letters for all signals variables and port
names reg is used in procedural block
Uppercase letters for constants and user-defined types eg `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names Use ram_addr for RAM address bus instead of ra
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P5
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P6
File Headers Include informational header at the top of every source
file including scripts Filename Author information eg name emailhellip Description of function and list of key features of the module Available parameters Reset scheme and clock domain Date the file was created and modified Critical timing and asynchronous interface
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P7
File Header Example DCTv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P8
Identifiers Naming Rule Begin with an alpha character (a-z A-Z) or
an underscore (_) and can contain alphanumeric dollar signs ($) and underscore Examples of illegal identifiers
34net ab_net n238
Up to 1023 characters long
Case sensitive eg sel and SEL are different identifiers
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P9
General Naming Conventions(13) Lowercase letters for all signals variables and port
names reg is used in procedural block
Uppercase letters for constants and user-defined types eg `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names Use ram_addr for RAM address bus instead of ra
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P6
File Headers Include informational header at the top of every source
file including scripts Filename Author information eg name emailhellip Description of function and list of key features of the module Available parameters Reset scheme and clock domain Date the file was created and modified Critical timing and asynchronous interface
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P7
File Header Example DCTv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P8
Identifiers Naming Rule Begin with an alpha character (a-z A-Z) or
an underscore (_) and can contain alphanumeric dollar signs ($) and underscore Examples of illegal identifiers
34net ab_net n238
Up to 1023 characters long
Case sensitive eg sel and SEL are different identifiers
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P9
General Naming Conventions(13) Lowercase letters for all signals variables and port
names reg is used in procedural block
Uppercase letters for constants and user-defined types eg `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names Use ram_addr for RAM address bus instead of ra
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P7
File Header Example DCTv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P8
Identifiers Naming Rule Begin with an alpha character (a-z A-Z) or
an underscore (_) and can contain alphanumeric dollar signs ($) and underscore Examples of illegal identifiers
34net ab_net n238
Up to 1023 characters long
Case sensitive eg sel and SEL are different identifiers
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P9
General Naming Conventions(13) Lowercase letters for all signals variables and port
names reg is used in procedural block
Uppercase letters for constants and user-defined types eg `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names Use ram_addr for RAM address bus instead of ra
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P8
Identifiers Naming Rule Begin with an alpha character (a-z A-Z) or
an underscore (_) and can contain alphanumeric dollar signs ($) and underscore Examples of illegal identifiers
34net ab_net n238
Up to 1023 characters long
Case sensitive eg sel and SEL are different identifiers
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P9
General Naming Conventions(13) Lowercase letters for all signals variables and port
names reg is used in procedural block
Uppercase letters for constants and user-defined types eg `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names Use ram_addr for RAM address bus instead of ra
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P9
General Naming Conventions(13) Lowercase letters for all signals variables and port
names reg is used in procedural block
Uppercase letters for constants and user-defined types eg `define MEM_WIDTH 16
Verilog is case sensitive
Meaningful names Use ram_addr for RAM address bus instead of ra
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P10
General Naming Conventions(23) Use clk for the clock signal
If more than one clock use clk as the prefix for all clock signals (clk1 clk2 clk_interface)
For active low signals use _n If the reset signal is active low use rst_n Similarly for active high signals use _p
For input of a register use _w For output of a register use _r For input signals use _i For output signals use _o
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P11
Example
assign reg1_w = data_iassign reg2_w = com1_o
assign com1_i = reg1_r
always (posedge clk_p) beginreg1_r lt= reg1_w
reg2_r lt= reg2_wend
always () begincom1_o = com1_i + 4rsquod5
end
data_i reg1_w reg1_r com1_i com1_o data_o
Reg1 Com Logic
reg2_w reg2_r
Reg2
Top
For connection
Logic
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P12
General Naming Conventions(33) Use [x0] (instead of [0x]) when describing
multi-bit buses A somewhat arbitrary suggested ldquostandardrdquo
Use parameter to improve readability module car (out in1 in2)
helliphelliphelliphellip parameter S0_STOP = 2rsquod0 S1_RUN = 2rsquod1
helliphelliphelliphellip
case (state) S0_STOP hellip
Donrsquot use HDL reserved words eg xor nand module
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P13
Use comments Use comments appropriately to explain
Brief concise explanatory Avoid ldquocomment clutterrdquondash obvious functionality does not need
to be commented Single-line comments begin with
Multiple-line comments start with and end with
Use indentation to improve the readability of continued code lines and nested loops eg
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P14
Module Instantiation Always use explicit mapping for ports use named
mapping rather than positional mapping
module_a ( clk s1_i s1_o s2_i s2_o)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P15
Use loops and arrays Using loop to increase readability
Loop is usually used as memory initialization for example
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P16
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P17
Finite State Machines FSM have widespread application in digital systems
Most frequently used in controller
Mealy Machine The next state and the outputs depend on the present state and the inputs
Moore Machine The next state depends on the present state and the inputs but the output depends on only the present state
N ex t S ta te an d O utp u tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ex t S ta teC om bina tion a l
Log ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tion a lLog ic
clock
clo ck
Moore m achine
Mealy m achine
N ext S ta te and O utpu tC om bina tiona l
Log ic
Inp u ts
S ta teR eg is te r
O utpu ts
N ext S ta teC om bin a tiona l
Lo g ic
Inp u tsS ta te
R eg is te rO utpu tsO utpu t
C om bina tiona lLog ic
clock
clock
Moore m achine
Mealy m achine
output = f (In CS) output = f (CS)
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P18
Modeling FSM in Verilog Sequential Circuits
Memory elements of States (S)
Combinational Circuits Next-state Logic (NL) Output Logic (OL)
Three coding styles (1) Separate S OL and NL (2) Combines NL+ OL separate S (3) Combine S + NL separate OL 1048782
Not recommendedMix the comb and seq circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P19
Style (1) Separate S NL OL
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P20
Style (2) Combine NL+OL Separate S
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P22
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P23
Reset Signal Use the reset signal to initialize registered signals
dct_r lt= 1rsquob0
dct_r lt= dct_w
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P24
Avoid Latches (12) Avoid using any latches in your design
Use a design checking tool (nLint) to check for latches in your design
Poor Coding Styles Latch inferred because
of missing else condition
Latches inferred because of missing assignments and missing condition
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P25
Avoid Latches (22) Avoid inferred latches
Fully assign outputs for all input conditions
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P26
Avoid Combinational Feedback
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P27
Sensitivity List (13) For combinational blocks the sensitivity list must
include every signal that is read by the process Signals that appear on the right side of an assign statement Signals that appear in a conditional expression
For simplicity Verilog 2001 supports always ()
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P28
Sensitivity List (23) Include a complete sensitivity
list in each of always blocks If not the behavior of the
pre-synthesis design may differ from that of the post-synthesis netlist
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P29
Sensitivity List (33) For sequential blocks
The sensitive list must include the clock signal If an asynchronous reset signal is used include reset in the
sensitivity list
Use only necessary signals in the sensitivity lists Unnecessary signals in the sensitivity list slow down
simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P30
Combinational vs Sequential Blocks Combinational logic
Use blocking (=) assignments Execute in sequential order
Sequential logic Use nonblocking (lt=) assignments Execute concurrently
Do not make assignments to the same variable from more than one always block Multiple Assignment
always() beginsum_1 = A + Bsum_2 = sum_1 + Cend
+
+
A
B
C
sum_1
sum_2
always(posedge clk) begin m1_r lt= m1_w m2_r lt= m2_wend
m1_w m1_r
clk
m2_w m2_r
clk
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P31
case Statement Fully specified verilog case statements result in a
single-level multiplexer Partially specified Verilog case statements result in latches
case (sel) 2rsquob00 outc = a 2rsquob01 outc = b 2rsquob10 outc = c default outc = dendcase
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P32
if-then-else Statement An if-then-else statement infers a priority-encoded
cascaded combination of multiplexers
if (sel == 2rsquob00) outi = aelse if (sel = 2rsquob01) outi = belse if (sel = 2rsquob10) outi = celse outi = d
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P33
case vs if-then-else Statements case statements are preferred if the priority-encoding
structure is not required The multiplexer is faster
if-then-else statement can be useful if you have a late-arriving signal Connect the signal to a in last slide
A conditional assignment may also be used to infer a multiplexer
assign z = (sel_a) a b
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P34
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P35
Register All Outputs For each subblock of a hierarchical macro design
register all output signals from the subblock Makes output drive strengths and input delays predictable
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P36
Related Combinational Logic in a Single Module
Keep related combinational logic together in the same module
R1clk
A B R2clk
C
R1clk
ABC R2clk
R1clk
R2clk
ABC
Bad
Better
Best
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P38
Outline Principles of RTL Coding Styles
Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis
Debugging Tool nLint
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P39
GUI nLint -gui amp
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P40
Import Design
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P41
Edit File
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P42
Lint -gt Run
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P43
Fix Warning 1
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P44
Search Rule Right click -gt Search Rule
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P45
No Error amp Warning
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P46
Check for Synthesizable (12) SpringSoft nLint
Check for correct mapping of your design Not so power in detecting latches
Synopsys Design Compiler Synthesis Tool The embedded Presto Compiler can list your flip-flops and
latches in detailsgt dv -no_guigt read_verilog yourdesignv
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
ACCESS IC LAB Graduate Institute of Electronics Engineering NTU
P47
Check for Synthesizable (22)
Checking latches using Design Compiler
