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Mc Lc:PN 1: ...................................................................................................................6

TN QUN V DL ........................................................................................ 6

1.1. M u .................................................................................... 61.2. Khi nim ................................................................................. 61.3. Nhng u im c phng php thit k h thng sbng ngn ng m t phn

cng HDL...71.4. Gii thiu ngn ng m t phn cng VHDL ..................................... 8.9

1.5. Code c HDL trongVerilog.10,11

PN 2 .................................................................................................................. 12

TM U V VERLO ................................................................................ 12

I. Tng qun v verilog ..................................................................... 12II. CHCNNG CC T VNG TRONG VERILOG ............................. 12

1. Khong trng............................................................................................................ 13

2. Ch gii .................................................................................................................... 133. Ch s: ..................................................................................................................... 13

4. T nh dnh: ........................................................................................................... 13

5. C php: ...................................................................................................................13

6. Ton t: .................................................................................................................... 13

7. T khVerilog: ....................................................................................................... 13

III.CC CNG C BN TRONG VERILOG ......................................... 14

1. Cc cng c bn: ...................................................................................................... 141.1. C php: ................................................................................................................14

1.2. V d: .................................................................................................................... 14

2. Cng buf, not: .......................................................................................................... 14

2.1. C php: ................................................................................................................14

2.2. V d: .................................................................................................................... 14

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IV. CC DNG D LIU................................................................. 15I. t gi tr: ................................................................................................................. 15

II. Wire: ........................................................................................................................16

III. Reg: ........................................................................................................................16

IV. Input, Output, Inout: .................................................................... 16I. Integer (S nguyn): ...................................................................... 17

II. Supply 0, Supply1: ..................................................................................................17

III. Time: ......................................................................................................................18

IV. Prmeter (Thm s): ............................................................................................ 18

V. TON T................................................................................. 19I. Ton t s hc: ......................................................................................................... 19

II. Ton t qun h:...................................................................................................... 19

III. Ton t bit_wire:.................................................................................................... 19

IV. Ton t logic:......................................................................................................... 20

V. Ton t bin i: ..................................................................................................... 20

VI. Ton t ghp: ......................................................................................................... 20

VII. Ton t dch: ........................................................................................................ 20

VIII. Ton t iu kin: ............................................................................................... 20

IX. Th t ton t: ....................................................................................................... 20VI.TON HNG ............................................................................ 21

I. Literls (dng k t): ................................................................................................. 21

II. Chn 1 phn t bit v chn 1 phn cc bit. ............................................................. 21

III. Gi hm chc nng: ............................................................................................... 22

IV. Wire, reg, v thm s: ............................................................................................ 22

VII. MODULES.............................................................................. 23I. Khai bo modules: .................................................................................................... 23

II. Ch nh lin tip: .................................................................................................... 23

III. Module instantiations: ............................................................................................24

VIII. KHUN MU HNH VI (BEHAVIORAL)..................................... 25I. Nhng ch nh theo th tc: .................................................................................... 25

II. Delay trong ch nh:............................................................................................... 26

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III. Ch nh khi: ........................................................................................................ 26

IV. Begin end: .......................................................................................................... 26

V. Vng lp for: ........................................................................................................... 27

VI. Vng lp while:...................................................................................................... 27

VII. Khi lnh if else if else:................................................................................ 27

VIII. Case: ....................................................................................................................27

IX. KHI ALWAYS V KHI INITIAL............................................... 28I. Khi lwys: ............................................................................................................. 28

II. Khi initil............................................................................................................... 29

X. HM ....................................................................................... 30I. Khai bo hm: ...........................................................................................................30

XI. CHC NNG LINH KIN ........................................................... 30I. Thnh ghi Edge_triggered, flip_flop, b m: .........................................................31

II. B cng:.............................................................................................................. 32

III. B cng, tr: .......................................................................................................... 32

IV. B m 3 trng thi: .............................................................................................. 32

V. Cc linh kin khc:.................................................................................................. 32

PN 3

MT S V D33I. Cu trc mt chng trnh dng ngn ng Verilog: ................................................ 33

1. V d 1: .................................................................................................................... 33

. Chng trnh tnh NOR cc bit c bin vo ........................................................... 33

b. M phng ................................................................................................................. 33

2. V d 2: .................................................................................................................... 34

. Chng trnh cng hi bin bn bit ......................................................................... 34

b. M phng ................................................................................................................. 34

3. V d 3: .................................................................................................................... 35

. Chng trnh gii m 2 sng 4 ................................................................................. 35

b.m phng...............36.4.vi d 437a. dn knh 4 sng 2..........37b.m phng..38

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5.v d 5

. Chng trnh i BCD sng by on ................................................................ 39.40

b. M phng ................................................................................................................. 41

6 V d 6....................................................................................................................... 42

. Chng trnh gim t 9 xung 0, hin th r led 7 on ..................................... 42,43

b.Mphng ................................................................................................................... 44

7 V d 7....................................................................................................................... 44

. Chng trnh tng t 0 n 9, hin th r led 7 on .......................................... 44,45

b. M phng ................................................................................................................. 46

PN 4 47i Tp: ..................................................................................... 47

TT SEQUENTL LO USN UDP DNVERILOG. ..47,48,49

Kt lun ........................................................................................................................ 50

Ti liu thm kho: ...................................................................................................... 51

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PN

TN QUN V DL1.1. M u

Ngy ny ngnh cng ngh ch to phn cng lun c nhng tph khng ngng. T cc mch in n gin n cc mch s, mchtch hp, kin trc mch tr nn ngy mt phc tp hn. Nh nhng uim hn hn so vi cc phng php phn tch, m hnh ho, thit k

mch s kiu truyn thng m phng php s dng cc ngn ng mphng phn cng( HDL-Hrd wre Description Lnguges ) ng trthnh mt phng php thit k cc h thng in t s ph bin trnton th gii. Trong khun kh phm vi c bi bo ny chng ti xingii thiu mt loi ngn ng m phng phn cng l VHDL (Veryhigh speed intergrted circuit Hrdwre Description Lnguge), loingn ng ch yu c s dng m phng phn cng trong cngngh CPLD, FPGA, ASIC

1.2 hi nim

- L ngn ng thuc lp ngn ng my tnh(computer language- Dng miu t cu trc v hot ng mt vi mch- Dng m phng, kim tra hot ng vi mch- Biu din hnh vi theo thi gian va cu trc khnggian ca mch

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- Bao gm nhng k hiu biu din thi gian v s1ng thi (time andconcurrence)

1.3. Nhng u im ca phng php thitk h thng sng ngn ng m phng phn cng (DL)

Ngy ny, cc mch tch hp ngy cng thc hin c nhiu chcnng do m vn thit k mch cng tr nn phc tp. Nhng

phng php truyn thng nh dng phng php ti thiu ho hmBoolean hy dng s cc phn t khng cn p ng c cc yucu t r khi thit k. Nhc im ln nht c cc phng php nyl chng ch m t c h thng di dng mng ni cc phn t vinhu. Ngi thit k cn phi i qu hi bc thc hin hon ton thcng: l chuyn t cc yu cu v chc nng c h thng sng biudin theo dng hm Boolen, su cc bc ti thiu ho hm ny t li

phi chuyn t hm Boolen sng s mch c h thng. Cngtng t khi phn tch mt h thng ngi phntch cn phi phn tchs mch c h thng, ri chuyn n thnh cc hm Boolen, su mi lp li cc chc nng, hot ng c h thng. Tt c cc bc nitrn hon ton phi thc hin th cng khng c bt k s tr gip noc my tnh. Ngi thit k ch c th s dng my tnh lm cng c

h tr trong vic v s mch c h thng v chuyn t s mchsng cng c tng hp mch vt l dng cng c Synthesis. Mt nhcim khc n c phng php thit k truyn thng l s gii hn v phc tp c h thng c thit k .Phng php dng hmBoolen ch c th dng thit k h thng ln nht biu din bi vitrm hm. Cn phng php d trn s ch c th dng thit kh thng ln nht ch khong vi nghn phn t.

Phng php thit k, th nghim, phn tch cc h thng s sdng cc ngn ng m t phn cng ni bt ln vi cc u im hn

hn vs dn thy th cc phng php truyn thng. S r i cngn ng m phng phn cng gii quyt c rt nhiu nhcim ln c cc phng php thit k trc y: Nu cc phng

php c i hi phi chuyn i t m t h thng (cc ch tiu v chcnng) sng tp hp cc hm logic bng ty th bc chuyn honton khng cn thit khi dng HDL. Hu ht cc cng c thit k dngngn ng m phng phn cng u cho php s dng biu trng

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thi( finite-state-mchine) cho cc h thng tun t cng nh cho phps dng bng chn l cho h thng tng hp. Vic chuyn i t cc

biu trng thi v bng chn l sng m ngn ng m phng phncng c thc hin hon ton t ng.

Nh tnh d kim tr th nghim h thng trong sut qu trnh thitk m ngi thit k c th d dng pht hin cc li thit k ngy tnhng gii on u, gii on ch vo sn xutth, do titkim c lng chi ph ng k bi t thit k n to r sn phmng nh mong mun l mt vic rt kh trnh khi nhng kh khn,tht bi.

Khi mi lnh vc c kho hc u pht trin khng ngng th sphc tp c h thng in t cng ngy mt tng theo v gn nhkhng th tin hnh thit k th cng m khng c s tr gip cu cc

loi my tnh hin i. Ngy ny, ngn ng m t phn cng HDLc dng nhiu thit k cho cc thit b logic lp trnh c PLDt loi n ginn cc loi phc tp nh m trn cng lp trnh cFPGA.

1.4. ii thiu ngn ng m t phn cng VDL

VHDL l ngn ng m t phn cng cho cc mch tch hp tc rt co, l mt loi ngn ng m t phn cng c pht trin dng cho

trng trnh VHSIC( Very High Speed Itergrted Circuit) c b qucphng M. Mc tiu c vic pht trin VHDL l c c mt ngnng m phng phn cng tiu chun v thng nht cho php thnghim cc h thng s nhnh hn cng nh cho php d dng cch thng vo ng dng trong thc t. Ngn ng VHDL c bcng ty Intermetics, IBM v Texs Instruments bt u nghin cu phttrin vo thng 7 nm 1983. Phin bn u tin c cng b vo thng8-1985. Su VHDL c xut t chc IEEE xem xt thnhmt tiu chun chung. Nm 1987 r tiu chun v VHDL( tiu

chun IEEE-1076-1987).VHDL c pht trin gii quyt cc kh khn trong vic phttrin, thy i v lp ti liu cho cc h thng s. Nh t bit, mth thng s c rt nhiu ti liu m t. c th vn hnh bo tr sch mt h thng t cn tm hiu k lng ti liu . Vi mt ngnng m phng phn cng tt vic xem xt cc ti liu m t tr nn d

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dng hn v b ti liu c th c thc thi m phng hot ngc hthng. Nh th t c th xem xt ton b cc phn t c hthng hot ng trong mt m hnh thng nht.

VHDL c pht trin nh mt ngn ng c lp khng gn vi

bt k mt phng php thit k, mt b m t hy cng ngh phncng no. Ngi thit k c th t do l chn cng ngh, phngphp thit k trong khi ch s dng mt ngn ng duy nht. V khi emso snh vi cc ngn ng m phng phn cng khc k r trn tthy VHDL c mt s u im hn hn cc ngn ng khc:

- Th nht l tnh cng cng: VHDL c pht trin di s botr c chnh ph M v hin ny l mt tiu chun c IEEE. VHDLc s h tr c nhiu nh sn xut thit b cng nh nhiu nh cungcp cng c thit k m phng h thng.

- Th hi l kh nng h tr nhiu cng ngh v phng php thitk. VHDL cho php thit k bng nhiu phng php v d phngphp thit k t trn xung, hy t di ln d vo cc th vin snc. VHDL cng h tr cho nhiu loi cng c xy dng mch nh sdng cng ngh ng b hy khng ng b, s dng m trn lp trnhc hy s dng mng ngu nhin.

- Th b l tnh c lp vi cng ngh: VHDL hon ton c lpvi cng ngh ch to phn cng. Mt m t h thng dng VHDLthit k mc cng c th c chuyn thnh cc bn tng hp mch

khc nhu tu thuc cng ngh ch to phn cng mi r i n c thc p dng ngy cho cc h thng thit k .

- Th t l kh nng m t m rng: VHDL cho php m t hotng c phn cng t mc h thng s cho n mc cng. VHDL ckh nng m t hot ng c h thng trn nhiu mc nhng ch sdng mt c php cht ch thng nht cho mi mc. Nh th t c thm phng mt bn thit k bo gm c cc h con c m t chi tit.

- Th nm l kh nng tro i kt qu: V VHDL l mt tiuchun c chp nhn, nn mt m hnh VHDL c th chy trn mi

b m t p ng c tiu chun VHDL. Cc kt qu m t h thngc th c tro i gi cc nh thit k s dng cng c thit k khcnhu nhng cng tun theo tiu chun VHDL. Cng nh mt nhmthit k c th tro i m t mc co c cc h thng con trong mth thng ln (trong cc h con c thit k c lp).

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- Th su l kh nng h tr thit k mc ln v kh nng s dngli cc thit k: VHDL c pht trin nhmt ngn ng lp trnh bcco, v vy n c th c s dng thit k mt h thng ln vi sthm gi c mt nhm nhiu ngi. Bn trong ngn ng VHDL c

nhiu tnh nng h tr vic qun l, th nghim v chi s thit k. Vn cng cho php dng li cc phn c sn.

1.5.ode cua DL trong verilog

/**

* A behavioural model of a pipelined MAC unit. The two 4-bitinputs are* multiplied in an 8-bit multiplier, with the result added to a 10-bit* accumulator. The number of pipe stages is set by the 'stages'parameter,* which defaults to 1.** RST Synchronous reset

* C Clock* A[3:0] Data Input* B[3:0] Data Input* Q[9:0] Accumulator output*/

module MAC1(input RST, CLK,input [3:0] A, B,output [9:0] Q);

parameter stages = 1;

reg [7:0] mul;

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reg [9:0] sum[stages-1:0];integer i;

always @(posedge CLK) begin

for(i=stages-1; i>0; i = i-1)sum[i] = sum[i-1];

if(RST)sum[0] = 0;

else beginmul = A * B;sum[0] = sum[0] + mul;

endend

assign Q = sum[stages-1];endmodule

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PN 2

TM U V VERLOI. TN QUN V VERLO

Verilog HDL l mt trong hi ngn ng m phng phn cngthng dng nht, c dng trong thit k IC, ngn ng ki lVHDL.HDL cho php m phng cc thit k d dng, s ch li, hocthc nghim bng nhng cu trc khc nhu. Cc thit k c mt trong HDL l nhng k thut c lp, d thit k, d tho g, v

thng d c hn dng biu , c bit l cc mch in ln.Verilog thng c dng m t thit k n dngThut ton (mt s lnh ging ngn ng C nh: if, cse,for,while).Chuyn i thnh ghi (kt ni bng cc biu thc Boolen).Cc cng kt ni( cng: OR, AND, NOT).Chuyn mch (BJT, MOSFET). Ngn ng ny cng ch r cchthc kt ni, iu khin vo/r trong m phng.

u trc chng trnh dng ngn ng Verilog// Khai bo moduleModule tn chng trnh (tn bin I/O); // tn chng trnh trngtn file.v.Input [msb:lsb] bin;Output [msb:lsb] bin;Reg [msb:lsb] bin reg;Wire [msb: lsb] bin wire;// Khi bo khi lwys, hoc khi initil. cc lnh Endmodule

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II. NN T VN TRON VERLO

Nhng tp tin vn bn ngun Verilog bo gm nhng biu hinthuc tnh t vng su y:

1. Khong trngKhong trng ngn nhng t v c th ch khong cch, khongdi, dng miv dng ng dn. Do , mt lnh c th rnhiu dng phc tp hn m khng c nhng c tnh c bit.

2. Ch gii

Nhng ch gii c th ch nh bng hi cch: ( ging trongC/C++)Ch gii c vit su hi du gch xin (//). c vit trn cngmt dng.c vit gi /* */, khi vit nhiu dng ch gii.

3. Ch s:

Lu tr s c nh ngh nh l mt con s c cc bit, gi tr cth l: s nh phn, bt phn, thp phn, hoc thp lc phn.V d 3b001, 5d30 = 5b11110,16h5ED4 = 16d24276 = 16b0101111011010100

4. T nh danh:

T nh dnh do ngi dng quy nh cho bin s, tn hm, tnmun, tn khi v tn trng hp. T nh dnh bt u bng mtmu t hoc ng gch di _ ( khng bt u bng mt con shoc $ ) v k c mi ch s c mu t, nhng con s v nggch di, t nh dnh trong Verilog th phn bit dng ch.

5. C php:

K hiu cho php:

ABDCEbcdef1234567890_$Khng cho php: cc k hiu khc -, &, #, @

6. Ton t:

Ton t l mt, hi, hoc b k t dng thc hin cc ton hngtrn bin. Cc ton t bo gm >, +, &, !=.

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7. T khaVerilog:

C nhng t m phi c ngh c bit trong Verilog. V d:assign, case, while, wire, reg, and, or, nand, v module. Chngkhng c dng nh t nh dnh. T kh Verilog cng bo

gm c ch dn chng trnh bin dch v System Tsk (h thngson tho) v cc hm.

. N N TRON VERLO

Cc cng logic c s l mt b phn c ngn ng Verilog. C hic tnh c ch r l: drive_strenght v dely.Drive_strenght ch sc bn c cng. bn ng r l s kt ni

mt chiu n ngun, k to nn s kt ni trong sut trns dn,kt thc l tng tr ko ln hoc xung. Drive_strenght thngkhng c ch r, trong trng hp ny bn mc nh lstrong1 v strong0 .Delay: nu dely khng c ch r, th khi cng khng c trhon truyn ti; nu c hi dely c ch nh, th trc tin lmiu t tr hon ln, th hi l tr hon xung. Nu ch c mtdely c ch nh, th khi tr hon ln xung l nh nhu.

Dely c b qu trong tng hp. Phng php c s tr honch nh ny l mt trng hp c bit c PrmeterizedModules. Cc thm s cho cccng c s phi c nh nghtrc nh dely.

1. Cc cng c bn:

Cc cng c bn c mt ng r, v c mt hoc nhiu ng vo.Trong cc cng, c php c th biu din bn di, cc t kho ccc cng: nd, or, nnd, nor.

1.1. C php:

GATE (drive_strength)#(delays)Tn t kh cng _tn (output, input_1, input_2, , input_N);Delay: #( ln, xung) hoc #ln_vxung hoc #( ln_vxung)

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1.2. V d:

And c1 (o, , b, c. d); // c 4 ng vo cng And gi l c1c2 (p, f, g); // v 2 ng vo cng nd gi l c2Or #(4,3) ig ( o, b, c); // cng Or c gi l ig, rise time = 4, fll

time = 3Xor #(5) xor1 (, b, c); // su 5 n v thi gin th = b xor c

2. Cng buf, not:

Cc cng ny thc thi m v o theo theo th t mh sn.Chng c mt ng vo, hi hy nhiu ng r. C php c th biudin bn di, t kho buf, not.

2.1. C php:

Tn t kh cng _tn (output_1, output_2, , output_N, input);2.2. V d:

Not #(5) not_1( ,c); // su 5 n v thi gin th = o cBufc1 (o, p, q, r, in); // b m 5 ng r v 2 ng rc2 (p, f, g);

IV. DN D LU

I. t gi tr:

Verilog bo gm 4 gi tr c bn. Hu ht cc dng d liu Verilogch ccgi tr su:0: mc logic 0, hoc iu kin si.1: mc logic 1, hoc iu kin ng.X: mc logic tu nh

Z: trng thi tng tr co.X v Z dng c gii hn trong tng hp (synthesis)

II. Wire:

M t vt liu ng dy dn trong mt mch in v c dng kt ni cc cng hy cc module. Gi tr c Wire c th c,nhng khng c gn trong hm (function) hoc khi (block).

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Wire khng lu tr gi tr c n nhng vn phi c thc thi bi1 lnh gn k tip hy bi s kt ni Wire vi ng r c 1 cnghoc 1 module. Nhng dng c bit khc c Wire:Wnd(wired_nd): gi tr ph thuc vo mc logicAnd ton b b

iu khin kt ni n Wire.Wor (wired_or): gi tr ph thuc vo mc logic Or ton b biu khin kt ni n Wire.Tri(three_stte): tt c b iu khin kt ni n 1 tri phi trngthi tng tr co.1. C php:Wire [msb:lsb] tnbin wire.Wand [msb:lsb] tn bin wnd.

Wor [msb:lsb] tn bin wor.Tri [msb:lsb] tn bin tri.2. V d:Wire c;Wand d;Assign d= a;Assign d= b;// gi tr d l mc logic c php And v b.Wire [9:0] A; // vect A c 10 wire.

III. Reg:

Reg (register) l mt i tng d liu m n ch gi tr t mtth tc gn k tip. Chng ch c dng trong hm v khi thtc. Reg l mt loi bin Verilog v khng nht thit l thnh ghit nhin. Trong thnh ghi nhiu bit, dt c lu tr bng nhngch s khng du v khng c k hiu ui m rng, c thchin m ngi s dng c ch y l s b hi.1. C php:

Reg [msb:lsb] tn bin reg.2. V d:Reg ; // bin thnh ghi n gin 1 bit.Reg [7:0] A; // mt vect 8 bit; mt bnk c 8 thnh ghi.Reg [5:0]b, c; // hi bin thnh ghi 6 bit.

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IV. Input, Output, Inout:

Nhng t kho ny biu th ng vo, ng r, v port hi chiu cmt module hoc tsk. Mt port ng r c th c cu hnh t ccdng: wire, reg, wnd, wor, hoc tri. Mc nh l wire.1. C php:Input [msb:lsb] port ng vo.Output [msb:lsb] port ng ra.Inout [msb:lsb] port ng vo,r hi chiu.2. V d:Module sample (b, e, c, a);Input ; // mt ng vo mc nh l kiu wire.Outputb, e; // hi ng r mc nh l kiu wire.

Output [1:0] c; /* ng r hi bit, phi c khi botrong mt lnhring*/Reg [1:0] c; // ng c c khi bo nh mt reg.

I. Integer (S nguyn):

Integer l mt bin nng. Trong tng hp chng c dng chyu cho vng lp, thm s, v hng s. Chng hon ton l reg.Tuy nhiu chng ch d liu bng nhng s c du, trong khi khi bo dng reg ch chung bng s khng du. Nu chng chnhng s m khng nh ngh thi gin bin dch th kch thcmc nh l 32 bit. Nu chng ch hng, s tng hp iuchnhcc s c kch thc nh nht cn thit cho s bin dch.1. C php:Integer tn bin nguyn;tn hng nguyn;2. V d:Integer ; // s nguyn n gin 32bit.

Assignb= 63; // mc nh l mt bin 7 bit.II. Supply 0, Supply1:

Xc nh ch ng dn ln mc logic 0 ( t), logic 1( ngun)theo th t nh sn.

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III. Time:

Time l mt lng 64 bit m c s dng cng vi $time, hthng tho tc ch lng thi gin m phng. Time khng ch tr tng hp v v th ch c dng trong mc ch m phng.

1. C php:Timebin time;2. V d:Time c;c = $time; // c = thi gin m phng dng in.

IV. Parameter (Tham s):

Mt Prmeter xc nh 1 hng s m c t khi bn cho v dc th l mt module. Cc ny cho php t c th s ch.1. C php:Parameterpr_1= gi tr, pr_2= gi tr, ;Parameter [gii hn] pr_3 = gi tr;2. V d:Parameter dd = 2b00, sub = 3b111;Parameter n = 4;Parameter [3:0] pr_2 = 4b1010;

reg [n-1:0] hrry;// mt thnh ghi 4 bt m rng c t bithm s n trn.always @(x)y = {{(add - sub) {x}}}if(x) beginstate = par_2[1];else

state =par_2[2];end.

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V. TON T

I. Ton t s hc:

Nhng ton t ny thc hin cc php tnh s hc. Du + v -

c th c s dng mt trong hi ton t n (-z) hoc kp (x -y).Ton t+, -, *, /, %.

II. Ton t quan h:

Ton t qun h so snh hi ton hng v tr v mt n bit l 0hoc 1.Nhng ton t ny tng hp vo dng c so snh. BinWire v Reg l nhng bin dng. V th, (-3b001) = (3b111) v (-

3b001) > ( 3b110) nhng nu l s nguyn th -1< 6.c ton t quan h=, = =, !=.

III. Ton t bit_wire:

So snh tng bit hi ton ton hng.c ton t~ (bitwire NOT), & (bitwire AND), | (bitwire OR), ^ (bitwireXOR), ~^ hoc ^~ (bitwire XNOR).

IV. Ton t logic:

Ton t logic tr v 1 bit n 0 hoc 1. chng ging nh ton tbitwire ch l nhng ton hng n bit. Chng c th lm vic trnbiu thc, s nguyn hoc nhm bit, v coi nhu tt c cc gi trkhng bng 0 l 1. Ton t logicc dng nhiu trong lnh iukin (if else), khi chng lm vic trn biu thc.Ton t

!(NOT), && (AND), || (OR)Wire [7:0] x, y, z;Reg a;if((x= = y)&&(z)) a=1;else a=! x;

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V. Ton t bin i:

C tc dng trn tt c cc bit c mt vect ton hng v tr vgi tr nbit. Nhng ton t ny l hnh thc t i s c ccton t bitwire trn.

c ton t~ (bin i NOT), & (bin i AND), ~&( bin i NAND), | (bini OR), ~|(bin i NOR), ^ (bin i XOR), ~^ hoc ^~ (bin i XNOR).

VI. Ton t ghp:

Dch ton t u bng ch s c cc bit c nh ngh bi tont thou hi.V tr cn trng s c in vo vi nhng s 0 cho chi trng hp dch tri hoc phi.Ton t> (dch phi).

VII. Ton t dch:

Ghp hi hoc nhiu ton hng thnh mt vect ln.Ton t{} (concatenation)Wire [2:0] x;

Wire [3:0] y, Z;To r nhiu bn so c mt mc chn.Ton t:{n{ mc chn }} n nhm th bn trong mt mc chn.

VIII. Ton t iu kin:

Ging nh C/C++. Chng nh gi mt trong hi biu thc c bntrong mt iu kin. N s tng hp thnh b cng (MUX).Ton t

(iu kin)? kt qu khi iu kin ng : kt qu khi iu kin si.IX. Th t ton t:

Nhng ton t trong mc ging nhu nh gi t tri sng phi

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Ton t Tn[ ] Chn bit, chn phn( ) Phn trong ngoc n!,~ Mc logic v bit_wire NOT

&, |, ~&, ~|, ^, ~^ Bin i: AND, OR, NAND, NOT, XOR,XNOR.

+, - Du ch s m s dng.{ } Ghp ni { 3b101,3b110} = 6b101110

{{ } } Th bn {3{3b101 } }=9b101101101*, /, % Nhn, chi, phn trm.

+, - Cng tr nh phn. Dch tri, phi.

= Du so snh. Bin Reg v wire c ly bngnhng sdng.

= =, != Bng v khng bng trong ton t logic.& Bit_wire AND, nd tt c cc bit vi nhu.

^, ~^ Bit_wire XOR, Bit_wire XNOR.| Bit_wire OR.

&&, || Ton t logic AND, OR.?: x = ( iu kin ) T:F

V.TON N

I. Literals (dng k t):

L ton hng c gi tr khng i m c dng trong biu thcVerilog. C hi dng k t l:hui: l mt mng c nhiu k t c t trong du .

h s: l nhng s khng i, nh phn, bt phn, thp phn,hoc s hex.1. php cc ch snF ddddTrong :n : s nguyn miu t s bit.

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F: mt trong bn nh dng su: b( s nh phn), o( s bt phn), d(s thp

phn), h( s hex).2. V d

time is// chui k t.267 // mc nh 32 bit s thp phn.2b01 // 2 bit nh phn.20h B36E // 20 bit s hex.o62 // 32 bit bt phn.

II. Chn 1 phn t bit v chn 1 phn cc bit.

y l s l chn mt bt n hoc mt nhm bit theo th t, tmt wire, reg hoc t thm s t trong ngoc [ ]. Chn 1 phn t

bit v chn 1 phn cc bit c th c dng nh l cc ton hngtrong biu thc bng nhiu cch thc ging nhu m cc i tngdliu gc c dng.1. C php:Tn bin [ th t bit].Tn bin [ msb: lsb].2. V d:Reg [7:0] a, b;

Reg [3:0] ls;c = a[7] & b[7];ls = a[7:4] + b[3:0];

III. Gi hm chc nng:

Gi tr tr v c mt hm c th c dng trc tip trong biuthc m khng cn gn trc cho bin reg hoc wire. Gi hmchc nng nh l mt trong nhng ton hng. Chiu rng bt cgi tr tr v chc chn c bit trc.1. C php:Tn hm(dnh sch bin).2. V d:Assign a = b & c & chk_bc(b, c);Function chk_bc;

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Input c, b;Chk_bc = b^ c;Endfunction

IV. Wire, reg, v tham s:Wire, reg, v thm s c th uc dng nh l cc ton hng trongbiu thcVerilog.

VII.MODULESI. Khai bo modules:

Mt module l bn thit k ch yu tn ti trong Verilog. Dng

u tin c khi bo module ch r dnh sch tn v port (cc is). Nhng dng k tip ch r dng I/O (input, output, hoc inout)v chiu rng c mi port. Mcnh chiu rng port l 1 bit.Su , nhng bin port phi c khi bo wire, wnd, , reg.Mc nh l wire. Nhng ng vo c trng l wire khi d liuc cht ben ngoi module. Cc ng r l dng reg nu nhngtn hiu c chng c ch trong khi lwys hoc initil.1. C php:

Module tn module (danh sch port);Input [msb:lsb] danh sch port ng vo;Output [msb:lsb] danh sch port ng ra;Inout [ msb:lsb ] danh sch port vo_ ra; cc lnhendmodule2. V dModule add_sub(add, in1, in2, out);Wire, reg, v tham sInput[7:0 ] in1, in2;Wire in1, in2;Output [7:0] out;Reg out; cc lnh khcEndmodule

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II. Ch nh lin tip:

Cc ch nh lin tip c dng gn mt gi tr ln trn mtwire trong mt module. l cc ch nh thng thng bn ngoikhi lwys hoc khi initil. Cc ch nh lin tip c thc hin

vi mt lnh gn (ssign) r rng hoc bng s ch nh mt gi trn mt wire trong lc khi bo. Ch rng, cc lnh ch nh lintip th tn ti v c chy lin tc trong sut qu trnh m

phng. Th t cc lnh gn khng qun trng. Mi thy i bnphi c bt c ng vo s lp tc thy i bn tri c cc ng r.1. C php:Wirebin wire = gi tr;Assignbin wire = biu thc;

2. V dWire [ 1:0 ] = 2b 01;Assign b = c &d;Assign d = x | y;

III. Module instantiations:

Nhng khi bo module l nhngkhun mu m n c to nnt cc i tng thc t ( instntition). Cc module n c bntrong cc module khc, v mi dn chng to mt i tng c

nht t khun mu. Ngoi tr l module mc trn l nhng dnchng t chnh chng. Cc port c module v d phi th nhngdnh ngh trong khun mu. y l mt l thuyt: bng tn, sdng du chm(.) .tn port khun mu ( tn c wire kt ni n

port). Bng v tr, t nhng port nhng v tr ging nhu trongdnh sch port c c khun muln instnce.1. C php:Tn instnce1 (dnh sch kt ni port );

Tn instnce2(dnh sch kt ni port);2. V d// nh ngh modulemodule and4(a,b,c);input [3:0]a,b;

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output [3:0]c;assign c = a&b;endmodule// module instantiations

wire [3:0] in1, in2;wire [3:0] o1, o2;// t v trand4 C1(in1, in2,o1);// tnand4 C2(.c(o2), .a(in1), .b(in2));

V. UN MU N V (EVORL)Verilog c 4 mc khun mu: Chuyn mch. Khng c cp n y. Cng. Mc trn d liu. Hnh vi hocth tc c cp bn diCc lnh th tc Verilog c dng to mt mu thit k mcco hn. Chng ch r nhng cch thc mnh c vc lm r

nhng thit k phc tp. Tuy nhin, nhng thy i nh n phngphp m h c th gy r bin i ln trong phn cng. Cc lnhth tc ch c th c dng trong nhng th tc.

I. Nhng ch nh theo th tc:

L nhng ch nh dng trong phm vi th tc Verilog (khilwys v initil). Ch bin reg v integers (v chn n bit/ nhm

bit c chng, v kt ni thng tin) c th c t bn tri du =trong th tc. Bn phi c ch nh l mt biu thc m c th

dng bt c dng ton t no.II. Delay trong ch nh:

Trong ch nh tr t l khong thi gin tri qu trc khi mtlnh c thc thi v bn tri lnh gn c to r. Vi nhiu chnh tr (intr-ssignment dely), bn phi c nh gi tr trc

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tip nhng c mt dely c t trc khi kt qu c t bn trilnh gn. Nu thm mt qu trnh thy i n cnh bn phi tnhiu trong khong thi gin t,th khng cho kt qu ng r.Dely khng c h tr bi cc cng c.

1. C php ch nh th tc:Bin = biu thc;Ch dnh tr:#t bin = biu thc;intra_assignment delay:

bin = #t biu thc.

III. Ch nh khi:

Ch nh khi (=)thc hin lin tc trong th t lnh c vit.Ch nh th hi khng c thc thi nu nh ch nh u chohon thnh.1. C php:Bin = biu thc;Bin = #t biu thc;#t bin = biu thc;

IV. Begin end:

Lnh khi begin end c dng nhm mt vi lnh m mtlnh c php c cho php. Bo gm function, khi lwys vkhi initil. Nhng khi ny c th c ty gi tn. V bo gmkhi bo reg, integer, thm s.1. C php:Begin: tn khiReg[msb:lsb] dnh sch bin reg;Integer [msb:lsb] danh sch integer;Parameter [msb:lsb] dnh sch thm s;cc lnhEnd

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V. Vng lp for:

Ging nh c/c++ c dng thc hin nhiu ln mt lnh hockhi lnh.Nu trong vng lp ch ch mt lnh th khi begin end c th b qu.

1. C php:For (bin m = gi tr 1; bin m = gi tr 2;

bin m = bin m +/- gi tr)begin lnh end

VI. Vng lp while:

Vng lp while thc hin nhiu ln mt lnh hoc khi lnh chon khi biu thc trong lnh while nh gi l si.1. C php:While (biu thc)Begin cc lnhEnd

VII. Khi lnh if else if else:

Thc hin mt lnh hoc mt khi lnh ph thuc vo kt qu cbiu thc theo su mnh if.C phpIf(biu thc)Begin cc lnhendelse if(biu thc)Begin cc lnhendelseBegin cc lnh

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end

VIII. Case:

Lnh cse cho php l chn trng hp. Cc lng trong khi

defult thc thi khi khng c trng hp l chn so snh gingnhu. Nu khng c s so snh, bo gm c defult, l ng, stng hp s to r cht khng mong mun.1. C php:Case (biu thc)Case 1:Begin cc lnhendCase 2:Begin cc lnhendCase 3:Begin cc lnhend

default:begin cc lnhendendcase

X. LWYS V NTL

I. Khi always:

L cu trc chn trong khun mu RTL (Register Transfer Level).Ging ch nh lin tc, y l trng thi tn ti m c thc thilin tc trong khi m phng. Ci ny cng c ngh l tt c cckhi lwys trong mt module thc thi mt cch lin tc. Khi

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lwys c th c dng trong cht, flip flop hy cc kt ni logic.Nu cc lnh c khi lwys nm trong phm vi khi begin endth c thc thi lin tc, nu nm trong khi fort join, chngc thc thi ng thi (ch trong m phng). Khi lwys thc

hin bng mc, cnh ln hoc cnh xung c mt hy nhiu tnhiu (cc tn hiu cch nhu bi t kh OR).C php:Always @(s kin 1 or s kin 2 or)Begin cc lnhendAlways @(s kin 1 or s kin 2 or)

Begin: tn khi cc lnhEnd

II. Khi initial

Ging nh khi lwys nhng khi initil ch thc thi mt ln tlc bt du c qu trnh m phng. Khi ny th tiu biu binkhi chy v ch nh dng sng tn hiu trong lc m phng.1. C php:

InitialBegin cc lnhEnd2. V dInitialBeginClr = 0;

Clk = 1;EndInitialBegin = 2b00;#50 = 2b01;

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#50 = 2b10;End

X. HM

Hm c khi bo trong phm vi mt module, v c th c git nhng lnh lin tc, khi lwys, hoc nhng hm khc. Tronglnh ch nh lin tc, cng c ch nh lin tc khi bt k cchm khi bo ng vo thy i. Trong chng trinh chng cch dng ti khi cn gi. Cc hm m t s kt ni logic, v khngto r cht. Do mt lnh if m khng else se m phng , mc dn c cht d liu nhng m phng th khng c. y l trnghp d c tng hp khng c m phng theo su. y l khi

nim tt m h hm, v vy chng s khng to r cht nu mhm c dng trong mt chng trnh.

I. Khai bo hm:

Khi bo hm l ch r tn hm, chiu rng c hm gi tr tr v,i shm d liu vo, cc bin (reg) dng trong hm, v thm scc b c hm, s nguyn c hm.1. C php:Function [msb:lsb] tn hm;Input [msb:lsb]bin vo;Reg [msb:lsb]bin reg;Parameter [msb:lsb] thm s;Integer [msb:lsb] s nguyn; cc lnhEndfunction

XI. NN LN NCht d liu (ltches): c suy nu mt bin, mt trong cc bitkhng c gn trong cc nhnh c mt lnh if. Cht d liucng c suy r t lnh cse nu mt bin c gn ch trong mtvi nhnh.

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Hon thin m c thc c dng lnh if tng hp cht vtht kh ch nh r rng. Theo l thuyt, mt s xc lp hp lnn c suy r t m Verilog.C php:

If else if else v cse.I. Thanh ghi Edge_triggered, flip_flop, b m:

Mt thnh ghi (flip_flop) csuy lun bng vic dng xung kchcnh lnhoc xung trong dnh sch s kin c lnh khi lwys.C php:Always @(posedge clk or posedge reset1 or nesedge reset2)BeginIf(reset1) beginCc ch nh resetendelse if(reset2) beginCc ch nh resetEndElse beginCc ch nh reset

EndII. B a cng:

c suy r bi vic gn mt bin m gi tr mi bin khc nhutrong mi nhnh c lnh if hoc cse. C th trnh cc ch nh vmi nhnh c th tn ti bng vic s dng ngoi nhng nhnhmc nh. Ch rng cht s c to r nu mt bin khng cgn cho cc iu kin nhnh c th tn ti. hon thin m c thc c, dng lnh cse to mu cng ln.

III. B cng, tr:

Ton t cng tr trong b cng tr m c chiu rng ph thucvo chiu rg c ton t ln hn.

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IV. B m 3 trng thi:

B m b trng thi c suy r nu bin c gn theo iu kingi tr tng tr co Z dng mt trong cc ton t: if, cse,

V. Cc linh kin khc:Hu ht cc cng logic c suy r t vic dngnhng ton hngtng ng c chng. Nh mt s l chn mt cng hoc mtthnh phn c th c gii thch r rng bng v d c th v sdng cc cng c s (nd, or, nor, inv) min l bng ngn ngVerilog.

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PHN 3:MT S V D

1.V D 1a.Chng trnh tnh NOR cc bt ca bin vomodule vdcong(in,out);input[3:0] in;output out;assign out= ~|in;endmodule

b. M phng

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2.v d

.chung trnh cng 2 bin 4 bt

. M PN

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3. v d 3a. Chung trnh gii m 2 sang 4

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.m phng

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4. v d 4a.B dn knh 2 sang 1

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. m phng

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5.v d 5.chng trnh chuyn i BCD sng 7 on

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b.m phng

6.v d 6a. Chng trnh gimt 0 xung 9, hin th ra led 7 on

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. m phng

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7. v d 7a. chng trng tng t 0 n 9 hin th ra led 7 on

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.m phng

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PHN 4:THIT K SEQUENTIALLOGIC USING UDP DNG VERILOG

//CC PHN PP TT

//N T T DN PN PP SU

D LACTH1 primitive latch_udp(q, clock, data) ;2 output q; reg q ;3 input clock, data;Table4 // clock data q q+

0 1 : ? : 1 ;0 0 : ? : 0 ;1 ? : ? : - ; // - = no change

5 endtable6 endprimitive

D Flip Flop

1 //-----------------------------------------------------2 // Design Name : dff_udp3 // File Name : dff_udp.v

4 // Function : D Flip Flop5 // Coder : Deepak Kumar Tala6 //--------------------------------------

---------------7 primitive dff_udp (q,clk,d);8 input clk,d;

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9 output q;10 reg q;11 table12 // clk d : q : q+

13 r 0 : ? : 0 ;14 r 1 : ? : 1 ;15 f ? : ? : - ;16 ? * : ? : - ;17 endtable18 endprimitive

SR Flip Flop

1 primitive srff_udp (q,s,r);2 output q;3 input s,r;45 reg q;

67 initial q = 1'b1;89 table10 // s r q q+11 1 0 : ? : 1 ;12 f 0 : 1 : - ;13 0 r : ? : 0 ;14 0 f : 0 : - ;15 1 1 : ? : 0 ;16 endtable1718 endprimitive

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JK Flip Flop

1 //-----------------------------------------------------2 // Design Name : jkff_udp3 // File Name : jkff_udp.v4 // Function : JK Flip Flop Using UDP5 // Coder : Deepak Kumar Tala6 //--------------------------------------

---------------7 primitive jkff_udp (q,clk,j,k);

8 input clk,j,k;9 output q;10 reg q;11 table12 // clk j k : q : q+13 r 0 0 : ? : - ;14 r 0 1 : ? : 0 ;15 r 1 0 : ? : 1 ;16 r 1 1 : 0 : 1 ;17 r 1 1 : 1 : 0 ;18 f ? ? : ? : - ;19 ? * ? : ? : - ;20 ? ? * : ? : - ;21 endtable22 endprimitive

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t lunVic ging dy phng php thit k s dng Verilog l rt cn thit i vi

sinh vin in t vin thng - cng ngh thng tin. i vi sinh vin th victrin khi nghin cu v ng dng c Verilog trnh by trn qu thc

rt c ngh. Hiu qu c vn khng phi ch l nm bt c nhng

tin b mi c kho hc ni chung, cng ngh ch to phn cng ni ring

m chnh Verilog s l mt phng thc h tr ging dy tht hu hiu, n

s gip cho cc mn hc vi xl, kin trc my tnh, tr nn bt tru tng

hn. Hin ny Verilog v ng c s dng rt ph bin trong cc

phng thc hnh th nghim in t-Vin thng cc trng i hc trn

th gii, v ng c nhiu cng ty in t - vin thng - tin hcs dng

thit k, pht trin cc sn phm c mnh.. Cc mn hc phng php

thit k s dng Verilog s trng b cho sinh vin mt phng php thit k

cc h thng s tin tin t sinh vin c th phn tch v thit k c cc

thit b, h thng in t s ng dng trong ngnh in t - vin thng c

hiu qu co. Do thi lm bi tp c hn v nhng hn ch khng trnh khic vic hiu bit cc vn d trn l thuyt l chnh nn bi tp c

nhm em chc chn khng trnh khi nhng thiu st . Chung em rt mong

c c nhng kin nh gi, gp c cc thy v cc bn bi tp c

chng em thm hon thin.

Su thi gin lm bi tp. Chng em rt r c rt nhiu kinh

nghim cho bn thn, cng l nh vo s ch dy nhit tnhc cc thyc v s gip c cc bn.

Chng em xin chn thnh cm n !

i

Nhm 14

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Ti liu tham kho1.Verilog Digital System Design

2.Introduction of Verilog3.Cadence VerilogXL Reference Manual

4.Synopsys HDL Compiler for Verilog Reference Manual

5.Diglad 10k10 Mannual

6.www.Syncad .com

7.TimingTool.com

8.www.maia-eda.net

9.http://tailieu.vn/xem-tai-lieu/tom-tat-bai-giang-verilog.174162.html

10. http://www.eej.ulst.ac.uk/guide/guide.html

11. http://www.eej.ulst.ac.uk/guide/syntax.html

12. http://www.eej.ulst.ac.uk/tutor/Vhdnotes.html

13. VHDL : Active Tutorial ALDEC Cooperation

14.http://www.xilinx.com

http://www.maia-eda.net/http://tailieu.vn/xem-tai-lieu/tom-tat-bai-giang-verilog.174162.htmlhttp://www.eej.ulst.ac.uk/guide/guide.htmlhttp://www.eej.ulst.ac.uk/guide/syntax.htmlhttp://www.eej.ulst.ac.uk/tutor/Vhdnotes.htmlhttp://www.xilinx.com/http://www.xilinx.com/http://www.eej.ulst.ac.uk/tutor/Vhdnotes.htmlhttp://www.eej.ulst.ac.uk/guide/syntax.htmlhttp://www.eej.ulst.ac.uk/guide/guide.htmlhttp://tailieu.vn/xem-tai-lieu/tom-tat-bai-giang-verilog.174162.htmlhttp://www.maia-eda.net/