Nhn S : 2. Lng c Thin3. L Thnh Giang4. Lng Th Thu Trang5. Hong Trng Giang6. Nguyn Xun Tng

1. Tm hiu chung v pipeline.2. Xung t (Hazard).

Xung t cu trc (Structural Hazard). Xung t d liu (Data Hazard). Xung t iu khin (Control Hazard).

3. Gii quyt xung t.4. Ngoi l5. K thut pipeline mi.

Super pipelining 8 tng. Super Scalar Dual pipeline.

Tun t Von Neumann v Pipeline?1.1. Cu trc tun t :

Thc hin cc lnh mt cch tun t. Theo 5 khu :

- IF (Instruction Fetch) : Nhn lnh- ID (Instruction Decode) : Gii m lnh- DF (Data Fetch) : Nhn d liu- EX (Execution) : Thc hin lnh- DS (Data Save) : Lu kt qu

Gi sMi lnh thc hin trong 1 chu k , mi

khu thc hin trong thi gian /5 Vi n lnh : Ttun t = *n

Cc lnh c thc hin lin tip nhau. Lnh trc thc hin xong mi n lnh sau. V vy xut hin khong thi gian ri (stall) gia

cc khu. K thut pipeline c a ra tn dng

nhng stall ny, t tng tc cho vi x l.

5 khu ca mt lnh trong MIPS:1. F (Fetch) : Nhn lnh.2. D (Decode) : Gii m lnh.3. X (Execution) : Thc hin lnh.4. M (Memory Access) : Truy nhp b nh.5. W (Result Write Back) : Ghi kt qu.

Trong trng hp khng c xung t c th tng tc vi x l ln 400%.

Tnh ton: Thi gian thc hin 1 cng on l /5. Thi gian thc hin 1 lnh l Thi gian thc hin 2 lnh l + /5 Thi gian thc hin 3 lnh l + *2/5 Thi gian thc hin n lnh l + *(n-1)/5

Tng qut : Tpipeline = + * (n-1)/m

Pipelining l mt k thut thc hin lnh trong cc lnh c thc hin theo kiu gi u nhm tn dng nhng khong thi gian ri (stalls) gia cc cng on (stages), qua lm tng tc thc hin lnh ca VXL.

Trn l thuyt, vic s dng k thut pipeline s lm tng tc VXL ln gn 400% nhng thc t,vic tng tc c bao nhiu cn ph thuc vo cc kiu xung t khc nhau di y.

Xung t cu trc (Structural Hazard)Xung t d liu (Data Hazard)Xung t iu khin (Control Hazard)

Xung t cu trc xy ra khi c 2 lnh cng c gng s dng cng 1 ngun ti cng 1 thi im.Khi 2 lnh cng ghi kt qu vo 1 thanh ghi:

ADD R1, R2, R3SUB R1, R4, R5

Khi c 2 lnh cng truy cp vo 1 nh ti cng mt thi im.

Khi c 2 lnh cng yu cu mt b tnh ton s hc (b cng, b nhn, b chia).

Xung t xy ra khi vic np lnh v c d liu t b nh din ra cng lc .

Nhng k hiu o chn vo tng trng cho chu k tr (stall cycles) s c s dng nu ta s dng b nh n lu tr c lnh vo d liu.

Khi c stage X v D u yu cu b cng, m ch c 1 b cng trong VXL.

2.2.1 RAW (Read after Write) Instruction 1: ADD R2, R1, R3 R2

2.2.2 WAR (Write after Read) Instruction 1: ADD R1, R2, R3 R1

2.2.3 WAW (Write after Write) Instruction 1: ADD R2, R1, R3 R2

Control Hazard xy ra khi c lnh r nhnh, do cn gi l Branch Hazard. Khi lnh r nhnh c yu cu thc hin, con tr b m chng trnh (PC) s chuyn ti a ch ch bng cch cng thm 4. Nu con tr chng trnh nhy ti ng a ch ch ca n, th r nhnh ny gi l nhnh Taken; trong trng hp ngc li gi l nhnh Untaken.

Khi lnh i c nhnh taken th PC s khng thay i nh bnh thng ti ht khu M (memory access), sau khi tnh ton v so snh a ch. Phng php n gin nht khc phc control hazard l gy tr kp thi trn pipeline pht hin nhnh cho n khu M, s dng gi tr mi ca PC.

Ta khng mong mun gy tr trn pipeline khi lnh ch c mt nhnh, v th tr khng xut hin ti sau khu ID v s thc hin nh hnh sau:

Ba chu k b ph mi nhnh l hao ph c ngha vi tn s r nhnh l 30% v 1 CPI l tng l 1, my tnh c tr r nhnh s t khong lng tng tc l tng ca pipeline.

Lnh nhnh F D X M W

Nhnh k tha F Stall Stall F D X M W

Nhnh k tha +1 F D X M W

Nhnh k tha +2 F D X M W

Nhnh k tha +3 F D X M

Nhnh k tha +4 F D X

Nhnh k tha +5 F D

Xung t (Hazard) l mt yu t quan trng nh hng trc tip ti tc ca VXL trong k thut Pipeline. Do vy, vic gii quyt xung t (Resolving Hazard) l rt cn thit. C mt s k thut gii quyt xung t ch yu sau y:

Chn tr.T chc li cc lnhS dng ng d liu ni c bit.Tomasulo.nh biu.

K thut chn tr c s dng kh hu hiu gii quyt cc xung t v cu trc cng nh v d liu:

V d:

Ta nhn thy xung t d liu xy ra khi lnh 1 cha lu kt qu vo R1 th lnh 2 thc hin tr R1 cho R5, y l xung t d liu RAW (c sau mi ghi).

Chn tr:

K thut chn tr ny hot ng kh n nh, tuy nhin vn cn cha tn dng c nhiu chu k nhn ri ca my, do hiu sut cha cao.

K thut ny i hi trnh dch phi d on c s ph thuc d liu gia cc lnh, qua thay i trt t thc hin lnh.

Xt v d: Tnh a:= b + c; d:= e - f

Ta thy s lnh NOP gim t 6 lnh xung cn 2 lnh -> ti u hn. Tuy nhin phng php ny i hi 1 trnh dch thng minh, chi ph cho

trnh dch v th s tng.

Gi tr ca bin s c cp nhp rt sm nh s dng ng d liu ni c bit. iu ny lm gim s chu k nhn ri trong pipeline v tng tc VXL

Internal Data Forwarding:

D liu s c lu b m ALUout sau pha X, v s c ghi ln thanh ghi trong pha M (hoc l trong pha W i vi lnh LW). Nh vic s dng b m ALUout ct d liu v s dng -> gii quyt c phn ln cc xung t v d liu cng nh cu trc -> s lm gim ng k s chu k nhn ri ca my -> tng tc xung nhp.

Phng n ti u cho v d trn kt hp s dng c T chc li cc lnh v ng d liu ni c bit

Thut ton Tomasulo c a ra vo nm 1967 bi Robert Tomasulo lm vic cho hng IBM. tng ca thut ton l s dng a ch Tag v bit trng thi nh du cc thanh ghi, qua bit c thanh ghi ang bn hay ri s dng cho ph hp.

S dng cc vector trng thi v bng t ch (reservation table) dnh du cc trng thi ca cc tng pipeline.

T xc nh c s chu k cn a d liu vo trnh xung t.

Ngoi l xy ra khi th t thc hin cc cu lnh b thay i khng mong mun.

Trong k thut pipeline, cu lnh c thc hin tng phn v khng th hon thnh trong vi chu k ng h. Cc lnh c th gy ra cc ngoi l m khin b my phi t b cu lnh trong pipeline trc khi n c hon thnh.

4.2.1 Cc kiu ngoi l :Chng ta s dng khi nim ngoi l ni v

cc trng hp sau: I/O device request (yu cu thit b I/O). Invoking an operating system service from user

program (gi mt dch v h iu hnh t ngi s dng chng trnh).

Tracing instruction execution (theo du s thc hin cu lnh).

Breakpoint (im ngt khi lp trnh vin yu cu ngt).

Integer arithmetic overflow (trn s hc).

FP arithmetic anomaly (d thng s hc du phy ng).

Page fault (not in memory) - t on trang (khng trong b nh).

Misaligned memory access (khng cn hng khi truy cp b nh).

Memory protection violation (vi phm vng nh bo v).

Using an undenined or unimplemented instruction (s dng cu lnh cha nh ngha hoc cha b sung).

Hardware malfuntions (s c phn cng). Power failure (thiu ngun).

4.2.2 Cc yu cu:Cc lung yu cu c th gy ra ngoi l:

Synchronous and asynchronous (ng b v khng ng b). User requested and coerced (ngi s dng yu cu v p buc). User maskable and user nonmaskable (c th che giu v khng

th che giu). Within and between instructions (bn trong v gia cc cu lnh). Resume and terminate ( phc hi li v chm dt).

t vn :V D: S t on trang trong ng ng dng DLX lm kt qu ca d liu cn a ra khng th xut hin trong bc MEM ca qu trnh thc hin cu lnh. Khi c s t on th mt vi cu lnh khc vn thc hin nhng chng khng th cho ra kt qu.

Do , phn t on trang phi c khi ng li v yu cu s can thip ca cc x l (nh h iu hnh).Chnh v th, pipeline phi c tt mt cch an ton, cng on thc hin nh li, v sau cu lnh phi c thc khi ng li ti ng vng m n thc hin.

Chnh v th hu ht cc ngoi l kh c 2 thuc tnh chng ta ng quan tm l: Chng xut hin bc no trong cc cu lnh

(vd: gia giai on EX v MEM). Chng c kh nng khi ng li hay khng.

4.3.1 Cc bc lu cc tng pipeline mt cch an ton:1. p cc cu lnh c vn trong pipeline vo c ngt

(IF) k tip.Khi xut hin vn , tt tt c vic ghi cho cc cu lnh t on v cc cu lnh trong pipeline. Vic c th thc hin bng cch t gi tr 0 ti cc cht ng ng ca tt c cc cu lnh trong pipeline. Khi ng vi cc cu lnh gy ra ngoi l; khng p dng cho cc pipeline trc cu lnh . Vic ny s bo v bt k cng on b thay i ca cc cu lnh cha c hon thnh trc khi ngoi l c kim sot.

1. Sau khi nhng ngoi l c kim sot, thng l khi H iu hnh nhn c iu khin, cc ngoi l v cc cu lnh sai s c nh du, n ngay lp tc lu tr trn b m chng trnh (PC). Gi tr lu tr ny s c s dng p li (gii quyt) nhng ngoi l sau .

Trong k thut pipeline, nhiu ngoi l c th xut hin ti cng mt chu k ng h do nhiu lnh c thc hin ng thi.

Pipeline stage

Problem exceptions occurring

IF Page fault on Instruction fetch;Misaligned memory access;Memory protection violation

ID Undefined or illegal opcodeEX Arithmetic exceptionMEM Page fault on Instruction fetch;Misaligned memory

access;Memory protection violationWB None

V d:

LW IF ID EX MEM WBADD IF ID EX MEM WB

Khi lnh LW trong cng on MEM v trong khi lnh ADD ang thc hin trong cng on EX, cc ngoi l page fault v arithmetic c th xut hin cng mt lc. Trng hp ny c th c kim sot bng cch ch gii quyt vi ngoi l page fault v sau khi ng li ngoi l. Ngoi l th hai s li xut hin sau khi khi ng li v n s c kim sot mt cch c lp.

Trong thc t, tnh hung khng n gin nh v d trn. Cc ngoi l s xut hin khng theo th t no; khi , mt cu lnh sau c th gy ra cc ngoi l trc khi cc cu lnh trc gy ra cc ngoi l. Xem xt li v d trn, ADD thc hin sau LW. LW gp ngoi l page fault nu chng trong cng on MEM, nhng lnh ADD cng c th gp page fault khi chng trong cng on IF.

Kt lun: Pipeline khng th kim sot c cc ngoi l khi chng xut hin cng 1 lc. Do chng s dn ti cc ngoi l xut hin khng theo th t pipeline

Yu cu t v d trn: pipeline yu cu phi kim sot ngoi l gy ra bi lnh LW trc lnh ADD.

Gii php: Phn cng s a tt c cc ngoi l c gy ra bi cc cu

lnh vo trong mt vector trng thi ngoi l kt hp vi cc cu lnh .

Vector ny tn ti xuyn sut trong pipeline cho ti khi cc cu lnh kt thc.

Nu c du hiu xut hin ca ngoi l no, th ngoi l s c thit lp trong vector trng thi.

Bt k mt tn hiu iu khin no m c th tin hnh vic ghi d liu u b tt (bao gm c vic ghi vo thanh ghi v ghi vo b nh). Bi v, bc MEM c th gy ra ngoi l, v phn cng phi chun b bo v vng thc hin khi s hon thnh nu xut hin ngoi l.

Khi cu lnh sang cng on WB (hoc ra khi MEM), vector trng thi c nh du. Nu c bt k mt ngoi l no c t vo, chng s c kim sot theo th t m chng xut hin. Vi s m bo ny, tt c nhng ngoi l c gy ra bi cu lnh th i s c xem xt trc cu lnh th i + 1.

Ti sao phi nghin cu (kim sot) ton t du phy ng? Cc ton t du phy ng kh c th c

hon thnh trong 1 hoc 2 chu k ng h. Do , s thc hin ca pipeline i vi ton t du phy ng (nu c) c nhng im c bit so vi dng DLX thng thng (IF, ID, EX, MEM, WB)

Gii quyt: gi s, cc cu lnh du phy ng cng nm trong pipeline ging nh cc cu lnh nguyn, nhng c 2 s thay i quan trng

1. Bc EX c th lp li nhiu ln bng s ln cn thit cho vic hon thnh s thc hin ca ton t.

2. S c thm cc khi chc nng du phy ng:

Tha nhn c 4 khi chc nng ring bit trong s hot ng ca DLX

Khi nguyn chnh, kim sot vic ti v lu cc ton t nguyn ALU v vic r nhnh.B nhn s nguyn v s FP.B cng s FP kim sot vic cng, tr v o ch s FP.B chia s nguyn v s FP.

FP s lp khi n bc EX. Sau khi Kt thc bc EX, chng s x l n MEM v WB hon thnh qu trnh thc thi.

Khu pipeline EX c mt s tr ng h ln hn 1.

m t dng pipeline ny, ta s dng latency ca khi chc nng v khong thi gian bt u: Latency: s lng cc chu k xen vo gia cu lnh

sinh ra kt qu v cu lnh s dng kt qu. Khong thi gian bt u: s lng cc chu k phi

tri qua gia ln a ra ca 2 ton t cng loi.

tr v thi gian khi to ca cc khi chc nng:

Khi chc nng tr Thi gian khi to

Integer ALU 0 1

Data memory (integer & FP loads) 1 1

FP add 3 1

FP multiply (also integer multiply) 6 1

FP divide (also integer divide) 24 25

MULTD IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB

ADD IF ID A1 A2 A3 A4 MEM WB

Bc c in nghing ch n ni d liu c yu cu.

Bc c in m ch n ni kt qu tn ti.

5.1 Superpipelining: (Siu ng dn) c s dng trong dng VXL MIPS

R4000. Tng s tng Pipeline t 5 ln 8 tng. Thi gian x l n lnh: T superpiplining = + (n - 1) * /8

Tc vi x l tng ng k so vi k thut Pipeline 5 tng, nhng cng v s tng tng m kh nng xy ra xung t cng cao hn

Cc VXL hin i bt u t dng Pen IV s dng k thut ng dn i (Dual Pipelining) tng tc ln gp nhiu ln so vi k thut Pipeline thng thng.

C th ly v d n gin khi ta tnh ton php tnh 14 * 47 + 5122, nu l k thut pipeline thng thng vn phi mt 3 bc l tnh 5122, sau tnh 14 * 27, ri cui cng cng 2 kt qu li. Nhng vi k thut ng dn i, 2 php tnh 5122 v 14 * 47 c thc hin cng 1 lc trn 2 pipeline khc nhau => gim c 1 cng on thc hin tnh ton