Lecture03 Ee474 Mos Models2

8/13/2019 Lecture03 Ee474 Mos Models2

1/28

Sam Palermo

Analog & Mixed-Signal Center

Texas A&M University

ECEN474: (Analog) VLSI Circuit DesignFall 2012

Lecture 3: MOS Transistor Modeling


2/28

Announcements

Lab 1 this week

Current Reading

Razavi Chapters 2 & 16

2


3/28

Agenda

MOS Transistor Modeling Large-Signal DC Model

Small-Signal AC Model

MOS Capacitors

3


4/28

Drawn & Effective Channel Lengths

The transistor gate overlaps both the source and drainregion by a length of LDdue to side diffusion in the

fabrication process This results in the effective transistor gate length, Leff,

being shorter than the drawn length, Ldrawn Throughout the remainder of the course, L will generally

refer to Leff 4

Ddrawneff LLL 2=

[Razavi]


5/28

Finite Output Resistance in Saturation

In saturation, as VDS is increased the channel

pinch-off point moves slightly towards the source

This phenomenon is called channel-lengthmodulation and is characterized by a parameter

5

[Sedra/Smith]


6/28

Finite Output Resistance in Saturation

The current will increase slightlywith VDSin saturation, resulting

in a finite incremental outputresistance

Note, the channel-lengthmodulation parameter is

inversely proportional to L 6

( )

( )

( )

( )

( ) ( )DSTnGS

oxn

D

DS

TnGS

oxn

D

DS

TnGS

oxn

TnGS

oxn

TnGSoxn

D

VVVL

WCI

L

L

VVV

L

WCI

VL

L

LVVL

WC

VV

L

LL

WC

VVLL

WCI

+=

=

+=

=

+

=

=

12

1

2

12

1

1

2

2

2

2

2

2

2

[Sedra/Smith]


7/28

TAMU-474-08 J. Silva-Martinez

- 7 -

OUTPUT RESISTANCE (SATURATION REGION)

Drain current

substrate

P+ P+

S G D

N+

B

Depletion region

Channel length modulation is a second

(unreliable) order effect!

(Badly) Represented in SPICE by using

or a more complex model.

Simulated and experimental results

might be off by more than 100%

Channel Length Modulation

[ ] [ ]DSTGSeffOX

D VVVL

WC

i +

122

Leff

Lch

0

VD

S

IDS

VGS2

=0

Measure this parameter!


8/28

MOS Large-Signal Output Characteristicwith Finite Output Resistance

8

[Sedra/Smith]

( )

( ) ( )DSTnGSoxn

D

DSDSTnGSoxnD

VVVL

WCI

VVVVL

WCI

+=

=

12:Saturation

5.0:Triode

2


9/28

MOS Large-Signal Transfer Characteristic

9

[Sedra/Smith]

( ) ( )DSTnGS

oxn

D VVV

L

WCI

+= 1

2

2


10/28

Impact of Bulk Voltage

10

[Razavi]( ) ( )

DSTnGS

oxn

D VVV

L

WCI

+= 1

2

2

00022

=++=

SBVTFSBFTT

VVVV


11/28

Large-Signal DC Response

11


12/28

Large-Signal DC +Small-Signal AC Response

12

For small-signal analysis, we linearize the response

about the DC operating point

If the signal is small enough, linearity holds and thecomplete response is the summation of the large-signalDC response and the small-signal AC response


13/28

Low-Frequency Small-Signal Model

13

[Razavi]


14/28

Transistor transfer characteristic is used to extracttransconductance, gm

Transconductance, gm

14

( )

( )Q

TGS

eff

OX

Qgs

D

m

TGSeff

OX

D

VVL

WC

v

ig

VVL

WC

I

=

=

2

2

Effects)g(NeglectinSaturationIn

[Sedra/Smith]


15/28

Transistor output characteristic is used to extract outputconductance, go

Output Conductance, go

15

( ) ( )

( ) D

Q

TGS

eff

OX

Qds

D

o

DSTGS

eff

OX

D

IVVL

WC

v

ig

VVV

L

WCI

=

+=

2

21

2

Effects)(IncludingSaturationIn

[Sedra/Smith]


16/28

The small-signal drain current changes with VBSmodulationdue to changes in VT

Body Transconductance, gmb

16

[Razavi]

[ ] SBFm

Qbs

T

Q

TGSeff

OX

Qbs

D

mb V

g

v

V

VVL

W

Cv

i

g +

=

22*

Effects)g(NeglectinSaturationIn


17/28

Low-Frequency Small-Signal Model

17

( )

( )

[ ]SBF

m

Qbs

T

Q

TGS

eff

OX

Qbs

Dmb

Q

TGS

eff

OX

Qds

D

Q

TGSeff

OX

Qgs

D

m

V

g

v

V*VV

L

WC

v

ig

VVL

WC

v

ig

VVL

W

Cv

i

g

+

=

=

=

22

2

20

[Razavi]


18/28

MOS Transistor Capacitances

181

1

CapJunctionBulk-Drain

CapJunctionBulk-Source

Cap(Fringing)OverlapDrain-Gate

Note,Cap(Fringing)OverlapSource-Gate

4CapBulk-Channel

CapChannel-Gate

00

msw

B

BX

jsw

jswm

B

BX

j

j

jswDjDDBJ

jswSjSSBJ

ovGDov

DoxovovGSov

F

subSieffCB

oxeffGC

V

CC

V

CC

CPCAC

CPCAC

WCC

LCCWCC

NqWLC

CWLC

+

=

+

=

+==

+==

==

==

==

==

[Razavi]


19/28

MOS Transistor Capacitances (Off)

19

SBJSB

DBJDB

CBGC

CBGCGB

ovGDovGS

ovGDovGD

CC

CC

CC

CCC

WCCC

WCCC

CapBulk-Source

CapBulk-Drain

CapBulk-Gate

CapSource-Gate

CapDrain-Gate

==

==+

==

===

===

[Razavi]


20/28

MOS Transistor Capacitances (Triode)

20

[Razavi]

CBSBJSB

CBDBJDB

GB

GCGSovGS

GCGDovGD

CCC

CCC

C

CCC

CCC

2

1CapBulk-Source

2

1CapBulk-Drain

0CapBulk-Gate

2

1CapSource-Gate

2

1CapDrain-Gate

+==

+==

=

+==

+==


21/28

MOS Transistor Capacitances (Saturation)

21

[Razavi]

CBSBJSB

DBJDB

GB

GCGSovGS

GDovGD

CCC

CC

C

CCC

CC

3

2CapBulk-Source

CapBulk-Drain

0CapBulk-Gate

3

2CapSource-Gate

CapDrain-Gate

+==

==

=

+==

==


22/28

MOS Gate Capacitors Response

22

[Razavi]Doxov

LCC Note,


23/28

MOS Source & Drain Junction Capacitors

23

[Razavi] ( )

( ) jswjjswjDBSB

DS

DS

CEWWECPCACCC

EWPP

WEAA

++=+==

+==

==

2Junction

2


24/28

Source/Drain Junction Perimeter CapsDisclaimer

Note, there is some ambiguity on how to model the source/drainjunction perimeter (sidewall) capacitance on the side of the gate

This is due to the channel occupying a portion of the sidewall area

Different textbooks present different approaches

The Razavi text conservatively assumes that the sidewall perimeter

capacitance is the same on all sides

The Johns/Martin text (used in 2010) optimistically sets the sidewallperimeter cap to zero under the gate

The correct answer is somewhere in the middle

This semester I will follow the Razavi method and assume that thesidewall perimeter capacitance is the same on all sides (even underthe gate)

I will try to make it clear on any problem description

24


25/28

MOS Source & Drain Junction Capacitors

25

[Razavi] ( )

( ) jswjjswjDBSB

DS

DS

CEWWECPCACCC

EWPP

WEAA

++=+==

+==

==

2Junction

2

( )

( ) jswjjswDjDDB

jswjjswSjSSB

D

S

D

S

CEWECW

CPCAC

CEWWECCPCAC

EW

P

EW

P

EW

A

WEEW

A

22

Junction

22Junction

22

2

22

2

22

++=+=

++=+=

+=

+=

=

=

=

Folding the transistorallows for approximatelyhalf the drain junctioncapacitance with a small

increase in source junctioncapacitance

Folding into2 fingers

Folding into 2 fingers & sharing drain


26/28


- 26 -

Other resistors: Source/Drain

Drain/Source Resistance

Drain/Source Resistance

In addition to the contact resistance ,

the diffusion resistance has to be

considered.

In SPICE, R[]is defined as RSH

( )

=

=

tW

LR

RW

LR

Rseries

[]R

series

P+

D/S

iD

Top view

iD

LR

W


27/28


- 27 -

Small Signal Model (Saturation region)

Small signal model (saturation region)

B

gogmbvbsgmvgs

B

D

CdbCgd

Cgs

Cbs

S

S

GD

[ ] [ ]

[ ]

[ ] [ ] bs

Qbs

Dds

Qds

Dgs

Qgs

D

Q

DSTGS

eff

OXD

FSBFTT

DSTGS

eff

OXD

vv

iv

v

iv

v

iVVV

L

WCi

VVV

VVVL

WCI

+

+

++

++=

+=

12

22

12

2

0

2

( )

( )

[ ]SBF

m

Qbs

T

Q

TGS

eff

OX

Qbs

Dmb

Q

TGS

eff

OX

Qds

D

Q

TGS

eff

OX

Qgs

Dm

V

g

v

V*VV

L

WC

v

ig

VVL

WC

v

ig

VVL

WC

v

ig

+

=

=

=

22

2

20 bsmbds0gsmDD vgvgvgIi +++


28/28

Next Time

MOS Transistor Modeling High-Field Short-Channel Effects

Spice Models

28

Documents

Lecture03 Ee474 Mos Models2