G-COE PICE International Symposium and IEEE EDS Minicolloquim onAdvanced Hybrid Nano Devices: Prospects by World’s Leading Scinetists

Tokyo Tech., October 4 and 5, 2011

Challenges of Heterogeneous Integration on CMOS

益 一 哉 Kazuya Masu異種機能集積研究センター

東京工業大学

ICE cube CenterTokyo Institute of Technology

masu@ieee.org http://masu-www.pi.titech.ac.jp

Outline

1 Introduction Why RF CMOS?1. Introduction Why RF CMOS?

2 Our RF CMOS development2. Our RF CMOS development

Why do we expect heterogeneous y p gintegration on CMOS ?

3. Our approach to heterogeneous integration: Novel wafer shuttle technique.g q

4. Summary

Recent mobile phone

Freq and wavelength

freq

Voice, Packets

FM TxOne seg. TV

Lower band Higher band

Courtesy of Hideyuki Saso, Vice President, Fujitsu

WL

Mobile phone 4

Wideband RF frontend that covers multiple wireless applications withmultiple wireless applications with only one chip is in highly required.

[1] OpenMoko

PA : Power AmplifierMIX : MixerLPF : Low Pass FilterLNA : Low Noise Amplifier

L and C limit operational frequency

5Mutiband/multimode transceiver

Many wireless standards (400MHz – 6GHz) Mobile phone 800MHz 1 5GHz 1 9GHz 2GHz Mobile phone 800MHz, 1.5GHz, 1.9GHz, 2GHz

(+700MHz, 900MHz, 1.7GHz for the new system)(+800MHz, 900MHz, 1.8GHz, 1.9GHz for GSM)

WLAN 802 11b/ Bl t th 2 4GH WLAN 802.11b/g, Bluetooth 2.4GHz WLAN 802.11a/n 4.9GHz – 5.875GHz GPS 1.2GHz/1.5GHz DTV 440MHz – 770MHz

User's viewpoint User wants to connect network whenever wherever whomever

One terminal User wants to connect network whenever, wherever, whomever,

and whatever. System viewpointy p

Improvement of frequency usage efficiencyMultiband/multimode wireless communication is

indispensable.

Miniaturization of MOSFET/CMOS

1T

Frequency [Hz]10

size[m]

e [V

]

1T

Volta

geft (MOSFET) THz Application

100G 1 6

5Millimeter application

10G 100n 4

3MOSFET generation

ft (bipolar)

1G 10n

3

2

100M 1n

1

0Frequency for personal wireless communication

Supply voltage100M

‘85 ‘90‘75 ‘80 ‘05 ‘10‘95 ‘00 ‘15 ‘20 ‘25

Year

0

Miniaturization and Diversification

Digital vs. Analog/RC LSI

What is difference?

Scaling 9

CMOS device miniaturization has brought High-speed/high-frequency, Low consumption power, andLow consumption power, and Chip area reduction.

Chi d ti i di tl l t d tChip area reduction is directly related to lowering cost. If there is not area reduction (= cost

reduction) miniaturization is meaninglessreduction), miniaturization is meaningless.Area reduction of circuit using miniaturized

devices is essential!

RF CMOS

RLId LL

Id

vout

D

GC vo t

D

GCvout

Svin CL

voutS

CL

Restive load Typical LNA using

Gain of R-load LNA is degraded at high freq

30

Restive load Typical LNA using LC resonance

Restive loadLC g g q

because of RC component. LNA has sufficient gain at

high freq using LCQ1-

drai

n / d

B

10

20

n (d

B)

LC

high freq using LC resonance.

dbV

@ Q

-10

0

Gai

n

Frequency / Hertz

100M 200M 400M 1G 2G 4G 10G 20G 40G 100G

f （Hz）

Digital vs. RF CMOS circuit 11

RF CMOS

m 800 m

RF CMOS

540 800 m

LNA（Low Noise Amp) VCO（Voltage Controlled Oscillator

Area reduction is essential in CMOS scaling. Passive devices such

Many Core108Tr/3mm2

as inductor, resistor (including wire) and capacitors consume large area. CMOS devices are miniaturized, however the passives are not miniaturized!

Challenge of analog/RF circuit design is to reduce the area penalty of passives; ideally elimination of passives.

Challenges in RF CMOS 12

RF CMOS has sufficiently high ft and fmax No need of scaled MOS. 0.18m/0.13m

CMOS is enough for GHz application.g pp Requirement of monolithic integration digital

modulation/demodulation and analog/RFmodulation/demodulation and analog/RF signal processing. Passives such as inductor prevent the chip area from reduction.prevent the chip area from reduction.

Challenges in RF CMOS 13

Two approaches

MiniaturizationHeterogeneous integ MiniaturizationScalingMore Moore

Heterogeneous integInteg with diverse

functionalities More MoorefunctionalitiesMore than Moore

RF using mature (0.35, 0.18m) CMOS RF/Analog/Digital one CMOS

Performance enhancement with other technologies such as MEMS

chip (SoC) Area reduction of RF is

MEMS. Integ with digital by SiP, 3D, etc. indispensable.

Our research style using shuttle service 14

Design-Ｂ

Design-Ｃ Shuttle serviceDesign-A

D i d i CMOS i it i PDK Designers design CMOS circuit using PDK (Process Design Kit) supplied from foundry.

Foundry fabricates CMOS circuit. Designer receive CMOS chip.

Designers evaluates CMOS circuits.

Worldwide Service Institutes

CMP: 1990

Europractice: 1989

CMC

MOSIS(USA)

(Canada)

VDECIDEC(Korea)

(Japan)ICC

imec Europractice

(EU) CMP(France)

(USA) VDEC

CIC (Taiwan)

(Japan)ICC(China)

MOSIS: 1980 DARPA ProjectMOSIS: 1980 DARPA Project1994 Self-supported

CMC Microsystems: 1984 IDEC (Integrated Circuit Design Education Center): 1995

VDEC (VLSI D i d Ed ti C t ) 1996

CIC (Chip Implementation Center): 1993, Hsinchu

VDEC (VLSI Design and Education Center): 1996University of Tokyo

ICC (IC Technology and Industry): 2000, Shanghai

Major IC Design and Chip Implementation Service Institutes

Worldwide Service Organizations 16

Country USA Canada France Japan China Korea Taiwan

Institutes MOSIS CMC CMP VDEC ICC IDEC CICEstablished

19801994 1984 1990 1996 2000 1995 1993

EDA Tool Ⅹ NA 7 9 5 16 17EDA Tool

Vendors Ⅹ NA 7 9 5 16 17

Fabricated Chips (#) NA 380 391 254 120+176 250 1621p

Processes Provided (#)

26 6 15 8 15 8 14

Advanced Process 40nm 65nm 40nm 40nm 90nm 40nm 40nm Packaging Packaging

Testing Ⅹ Ⅹ

Training Training Coursed Ⅹ NA Ⅹ NA

Source: 2009 CMP Annual ReportRemark： ：Fair Service; ：Excellent Service ;Ⅹ ：No Service。

Outline

1 Introduction1. Introduction

2 Our RF CMOS development2. Our RF CMOS development

Why do we expect heterogeneous y p gintegration on CMOS ?

3. Our approach to heterogeneous integration: Novel wafer shuttle technique.g q

4. Summary

Challenges in RF CMOS 18

Two approaches

MiniaturizationHeterogeneous integ MiniaturizationScalingMore Moore

Heterogeneous integInteg with diverse

functionalities More MoorefunctionalitiesMore than Moore

RF using mature (0.35, 0.18m) CMOS RF/Analog/Digital one CMOS

Performance enhancement with other technologies such as MEMS

chip (SoC) Area reduction of RF is

MEMS. Integ with digital by SiP, 3D, etc. indispensable.

RF CMOS

RLId LL

Id Id

vout

D

GC vo t

D

GC

DG

vivoutS

vin CLvout

SCL

Restive load

voutS

vin

Typical LNA using

Gain of R-load LNA is degraded at high freq

30

Restive load Typical LNA using LC resonance

Restive loadLC g g q

because of RC component. LNA has sufficient gain at

high freq using LCQ1-

drai

n / d

B

10

20

n (d

B)

LC

high freq using LC resonance.

Our approach: CMOS-inverter base circuit

dbV

@ Q

-10

0

Gai

n

inverter base circuit components.

Frequency / Hertz

100M 200M 400M 1G 2G 4G 10G 20G 40G 100G

f （Hz）

Breakthroughs 20Scalable, Multi-band, Wide-band,

Digitally Controllable, Universal Discrete time processingWide-band

LPF AGC A/DLNA

Zo=50Ω?

S/H

Discrete time processingWide band

LPF AGC A/D

nd L

SILNA

ADBPF DCO

ADPLL

PD Count

I QBPFS/H

Bas

ebanAD

PLLBPF SW

DUPDCO

FN

PD

BPF B

PABPF

Low loss（MEMS?）

MOD

Digital enhanced self-compensation circuit

（MEMS?） Frequency → Time base processingDA function

(bias control, characteristics tuning, yield enhancement, linearity control, etc. )

Our recent work of scalable RF CMOS in 2008-201021

Scalability Discussion of scalability of the conventional topology

① LNA Wid b d i Ch H & ti f d b k① LNA Wideband using Cherry-Hooper & active feed-back

② LNA+VGA High-gain LNA+VGA by multi-stage inverterGain control using MOS-SW

③ Ring-VCO Low phase technique using Injection-lock and latched inverter

PLL using ring④

PLL using ring-VCO Freq synthesizer using PLL combination

⑤ PA Stacked CMOS for high-power output

⑥RF modulation block

RF signal generation using time-to-analog conversionQPSK signal generation using phase selection and

injection lock techniques

⑦RF demodulation block Passive mixer (on going)

⑧ Power supply On-chip LDO

Inverter base LNA 22

mfgofr

Active feedback for wideband

1mg 2mg1fR

r3mg 4mg

2fR

vvin

1or 2or

~sv

sr3or 3or

Cherry Hooper configuration Output buffer

voutSupply voltage: 1.1 VArea: 40 x 26 m2

20

10

0

-10利得

S21

(dB)

Vdd=1.30V

Vdd=1.25V

Vdd=1.20V

Vdd 1 15V

NF

(dB)

Vdd=1 30V

Vdd=1.10V

Vdd=1.20V

-20

利

Vdd=1.10V

Vdd=1.15V Vdd 1.30V

周波数 (GHz)1 10 202 3 5

周波数 (GHz)1 5 10 202 3

Performance of Scalable RF CMOS LNA

Injection locked differential VCO 24

Features (180nm CMOS process) 4-satage Ring-VCO

I/Q signal generation (0°, 90°, 180°, 270°) Half Integral subharmonic Injection locking

High freq resolution (40MHz)High freq resolution (40MHz)Low-phase noise (comparable to LC-VCO)(120dBc/Hz@1MHz offset)

Current controlWideband operation (1-2GHz)

Injection lock performance of D-VCO 25 Chip photo

Ring-VCO performanceOsc freq (free running):1.0G － 2.2GPower: less than 62mWPhase noise@1MHz offset

: 102dBc/Hz @1 44GHz

Freq performance (ref:80MHz)

:-102dBc/Hz @1.44GHz

Ref: 200MHz

整数倍×fREF

q p

z)

2.1

2.3

250ps

80M×23.52.2

2.4

(GH

z)

Free running250ps

半整数倍

×fuenc

y (G

Hz

Free running1 5

1.7

1.9 12.5nsinjection signal80M×24

80M×23

80M×22.5

1 6

1.8

2.0

Freq

uenc

y

g5ns

injection signal200M×10

200M×9

200M×9.5

200M×8.5

×fREF

Freq

u

Injection-locked

1.1

1.3

1.5

1.2

1.4

1.6O

scill

atio

n Injection locked

0 0.3 0.6 0.9 1.2 1.5 1.8

Control Voltage (V)

0.90 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

1.0

Control Voltage (V)

Phase noise of injection locked D-VCO 26 PN@1MHz offset@1.44GHz

-121dBc/Hz ( input pulse width:250ps 40MHz ): 20MHz resolution127dBc/Hz (input pulse width 250ps 80MHz) 40MHz resolution

−40-127dBc/Hz (input pulse width: 250ps 80MHz): 40MHz resolution

Lowering PN by injection-locking

−80

−60

se GH

z)

Lowering PN by injection locking

−100

ase

nois

z @

1.44

G

Free running

80MHz meas 40MH

25dB

−140

−120

Pha

(dB

c/H

z 80MHz meas. 40MHz meas.

80MHz est.40MHz est.

−160

(

80MHz ref.

40MHz ref

102 103 104 105 106 107−180

Offset frequency (Hz)

40MHz ref.

PLL using ring-VCO 27

PLL using injection-locked ring-VCO

(a) ２ステージPLL回路の構成 (b) 90nmCMOSによる試作チップ

ｆo = 6.1 GHz ｆo = 9.5 GHz

(c) 6.1 GHz 発振時 (d) 9.5 GHz 発振時 (e) 位相雑音特性（6.1 GHz）

Challenges in RF CMOS 28

Two approaches

MiniaturizationHeterogeneous integ MiniaturizationScalingMore Moore

Heterogeneous integInteg with diverse

functionalities More MoorefunctionalitiesMore than Moore

RF using mature (0.35, 0.18m) CMOS RF/Analog/Digital one CMOS

Performance enhancement with other technologies such as MEMS

chip (SoC) Area reduction of RF is

MEMS. Integ with digital by SiP, 3D, etc. indispensable.

Purpose 29

Zout = 5Ω of PA matching with 50Ω of antenna required L and C tuning range at 0 8~6GHzrequired L and C tuning range at 0.8~6GHz

freq (GHz) L (nH) C (pF)

Impedance

freq (GHz) L (nH) C (pF)0.8 3.0 12.06 0 0 4 1 6

P V i bl i d t f id b d RF f t d

matching6.0 0.4 1.6

Purpose： Variable inductor for wideband RF-frontend

Variable inductor requirementsVariable inductor requirements・Wide inductance tunable range for wideband operation ・High Q factor to reduce loss・High Q factor to reduce loss・High self resonant frequency for higher available frequency

N-bit control variable inductor 30

Controlling inductance with N switches Decreasing inductance by switching onDecreasing inductance by switching onSwitch type variable inductor can easily improve tunabilityHigh resolution with fewer switches eg) 8 value with 3 switchesHigh resolution with fewer switches eg) 8 value with 3 switches

CMOS process can realize this but loss is large

Switches and inductors with lower loss can be achieved by using MEMSy g

Thick metal and movable structure

Planar solenoidal inductor 31

space:16μm

Width:20μm

thickness:15μm

metal2viametal1

This shape hasCapability of attaching switch depending on number of turn Large L+mutual and small L-mutual to improve Q-factor

Fabricated test inductors 32

Metal （Au）MEMS processMetal （Au）Two metal layersSubstrate:1kΩ・cmSubstrate:1kΩ・cm

2 bit control2-bit controlFour test inductorswere fabricatedwere fabricated

Measurement results of inductance 33

1

Tunability is 230%

4-turns 3-turns 1-turn2-turns

Measurement results of Q-factor 34

4-turns 3-turns 1-turn2-turns

Comparison with other works 35

[1]: K Okada TED 2006 [2]: D H Choi Transducers 2009 [3]: P Park LED 2004[1]: K. Okada, TED, 2006. [2]: D. H. Choi, Transducers, 2009. [3]: P. Park, LED, 2004.[4]: J. Kim, TMTT, 2009. [5]: M. Rais-Zadeh, JMEMS, 2008. [6]: A. Shirane, JJAP, 2011.[7]: I. E. Gmati, mnl, 2010. [8]: S. Chang, LED, 2006. [9]: V. M. Lubecke, TMTT, 2001.

Outline

1 Introduction1. Introduction

2 Our RF CMOS development2. Our RF CMOS development

Why do we expect heterogeneous y p gintegration on CMOS ?

3. Our approach to heterogeneous integration: Novel wafer shuttle technique.g q

4. Summary

How to fabricate functionalities on CMOS 37

Issues Do we prepare process equipment? If we have process ability, can we fabricateIf we have process ability, can we fabricate

the functionalities on CMOS chip ? Chip sizes are several mm2.sizes are several mm .

How do we collaborate ? (from the viewpoint of circuit design researcher)of circuit design researcher)

Pre-CMOS and Intermediate- CMOS

Intermediate- CMOSPre- CMOS (MEMS first)

CMOS Movable CMOS Movable

ure

SiStru

ctu

Si Poly-SiS

・Sealing/Packaging・Low Voltage

・LSI Multilevel Interconnection・Large Chip Sizem

ents

g・MOS Reliability・Sacrificial Film Etching

g p

equi

rem

g（SiO2 or SiGe etc.)R

e

Post- CMOS (CMOS-first and MEMS last)

CMOS MovableEtching from Surface

CMOS MovableEtching from Back Side

CMOS Movable CMOS Movable

uctu

re

SiStru

Dielectric & bulk etch Bulk etch

tsre

men

t

・Sealing/Packaging・Low Voltage

・Plasma Damage・Large Chip Size

Req

uir

・MOS Reliability

Toward open collaboration

Novel wafer shuttle service for heterogeneous integration 40

Design-ＢDesign-Ｃ

Design-C

Design-A

Designers receive their own

Design-A Design-B

Designers receive their own circuit as chips.Another functions such as

sensor MEMS photonics fsensor, MEMS, photonics etc. cannot be fabricated on the chip. So far, CMOS processed

With novel masking technique, wafers can be provided to each designer. In wafer-A, another designer’s area are maskedp

wafer cannot be provided because another designer’s area cannot be masked.

masked. Sensor, MEMS, and photonics can be

fabricated or implemented on CMOS wafers!

Conventional shuttle service The novel wafer shuttle has been developed by

Tokyo Tech/NTT-AT collaboration.

Post CMOS 41

MEMS(functionalities)-first is suitable for mass-production type device such as acceleration sensor, pressure sensor, , p ,DMD, etc. cf. DRAM, Flash, MPUPost process can open the door to variousPost process can open the door to various

field researchers: circuit, process, bio engineers.New wafer shuttle technologyNew wafer shuttle technology

Detail of wafer shuttle

0.35μm standard CMOS with 20-V MOSFET, 6 inch waferArea designed by another designer isArea designed by another designer is

completely masking by the blind process.D i d i t ti ltiDesign and process integration consulting is available thru Tokyo Tech. Standard MEMS is also available.ＰＤＫ is distributed thru ＶＤＥＣ UnivＰＤＫ is distributed thru ＶＤＥＣ, Univ.

Tokyo

CMOS/MEMS standard process

CMOS-MEMS

MEMS

Poly-SiN+

Poly-SiP+N+ P+ N+ P+ N+ N+

ゲート ゲート

NMOS PMOS Bipolar

BiCMOS

Example of CMOS-MEMS

10 µmLower electrode

Upper electrodesealing MEMS

protuberance

Si基板

space

CMOSLSI

MEMS

Si基板

Integrated finger print sensor. Photo: Courtesy of NTT Micro integration Lab.

First wafer shuttle

Contributors More than 5 universities More than 3 research group in Tokyo Tech.

Fields Photonics MEMS RF MEMS Sensors (bio, Hall effect)

Tape out in Sept, 2011. Wafer will be delivered Tape out in Sept, 2011. Wafer will be delivered in Dec. 2011

Circuit designer provided IPsCircuit designer provided IPs.

Summary

RF CMOS developments: Scalable RF CMOS using miniaturized

CMOS Use of functionalities such as RF MEMS

inductorinductorWafer shuttle technology First wafer will be delivered in Dec. 2011. Fundamental circuit IPs will be handle by ICE

cube center, Tokyo Tech. These IPs will helpful for collaboration of different field researchers.