Digital System Design Course Outline Week Course Speaker Note 1st

(2/25) Overview DSD Course Prof. Wu Introduction 2nd (3/4) Overview of Verilog HDL thinking Hw0(+0.5%) 3rd (3/11) Modeling and Verification thinking Hw1(5%) 4th (3/18) Behavior Models thinking Hw2(5%) 5th (3/25) Design of Combinational Circuits thinking 6th (4/1) MIPS CPU (I) chihhao Lab1(12%) 7th (4/8) Design of Sequential Circuits thinking 8th (4/15) Q & A thinking 9th (4/22) Midterm Examination 期中考週 10th (4/29) MIPS CPU (II) chihhao Lab2(12%) 11th (5/6) Synthesis (I) thinking Proposal 12th (5/13) MIPS CPU (III) chihhao 13th (5/20) Synthesis (II) thinking 14th (5/27) Advanced concept thinking Check point 15th (6/4) FPGA(I) linyan Lab3(3%) 16th (6/11) FPGA(II) linyan Lab4(3%) 17th (6/17) Final project report and demo 18th (6/24) Final project report and demo 期末考週