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אא
אאאã¹]<gè…‚jÖ]æ<ËÖ]<Üé×Ãj×Ö<íÚ^ÃÖ]<퉉ö¹]
אאאא
١٤٧١٤٧אא
١٤٧ א א א
א
،،אא،אW
אאאאאאאאאאא א א א א א א ،א
אאאאאא،אאאאאא
אאאK
אאאאאאא א ،א אא
א ، א א א אא אא،אאאאאאאאאאאאאאאאא
א א ،א אא،אאK
א א ? א ? ? ?
אאאאאאאK
אאאאאאא،א،אאאא
אאאאאK
، א אאאאK
אאאא
١٤٧ א א
א
אאאאKKK،א،אאאאאא
אאאKאאאאאא
א،אא،אאאאאאאאאאאא
אאאKאאאאא،אאאאא،אאא،אאא
אאאאאאאאאאאKאאאאא
אאאאאאאאKאאאאא،אא
אא،א،אאKאאאא،،
אאאא،אאאK
،אKKKKKK
אאאא
אא
אאאã¹]<gè…‚jÖ]æ<ËÖ]<Üé×Ãj×Ö<íÚ^ÃÖ]<퉉ö¹]
אאאא
א
א
١
א١٤٧ א א א
אא א
- ١ -
אאא
אאW• אאאK • אאK • אאאאאאאK • אאאאאK • אאאאאK
א١٤٧ א א א
אא א
- ٢ -
١J١Introductionא
))Binary Number SystemאאאאאKאאאאאאאא) Digital Electronic Circuits(K
אא،אאאא)Decimal Number System(אKאאא
אאאאאא)Octal Number System(אאא)Hexadecimal Numbering System(K
אאאאאאאאאאאאאאKאאא
אאאאאאאKאאאאאW
١KאK٢KאאאK٣KאאאאאאK٤KאאאאK٥KאאאאאK
אאאא)Digit(
א)Number(،)Symbol(אאאאא،א)0,1,2,3,4, ... , 8,9(אאא
אאאאאאאא،אאאאא،א)14(אאא)123(،א
אאא14(א()1,4(אאאא)123()1,2,3()6(א
אK
א١٤٧ א א א
אא א
- ٣ -
١J٢אאא Decimal Numbering Systemאאאאאאאא
אאאאKאאאא)10(10א)10(
0,1,2,3,4,5,6,7,8,9 Kאא)Positional Weight(אא)128(
אא)8(אאFאE،אאאא1) 8 × 1 = 8(אא،)2(א
אFאאEאאא10 )2 × 10 = 20(،אאF1EאאFאE
אאא100) 1 × 100 = 100(Kא،אאאאאW
(1 × 100) + (2 × 10) + (8 × 1) = 100 + 20 + 8 = 128
אאאF10Eאאאאא10א 100 = 1W
........ 105 104 103 102 101 100
א128W 1 2 8
אאאא 102 101 100 1 × 102 + 2 × 101 + 8 × 100 (128)10 = 100 + 20 + 8
אא)128(אא10אא)Subscript(אאאאK
א١٤٧ א א א
אא א
- ٤ -
אאאאאאא10-1W
102 101 100 • 10-1 10-2 10-3 ........
١J٣אאאBinary Numbering Systemאאאאא )2()2(
א)1,0( .אאאאאאא)2(W
..... 24 23 22 21 20 אאאאW
..... 16 8 4 2 1 א11001(א(W
24 23 22 21 20 1 1 0 0 1 = (1 × 24) + (1 × 23) + (0 × 22) + (0 × 21) + (1 × 20)
= 16 + 8 + 0 + 0 + 1 = (25)10
אא،אאאאא
אאאאא(2)אאאא2(11001)אK
אאאאאW
אא)Bit(W אא(Bit)א)Binary Digit (אאאאאKאאאFאEא
א،א2(1001)א)4-bits(א(1101101)2)7-bits(אK
אא (Decimal Point)
א١٤٧ א א א
אא א
- ٥ -
אא)Number of Binary Combinations(W אאאאאא)bits(K
אאאW N = n2
WN= אאא n= א)bits(
אא(2)אאW N = 22 = 4
אא(3)אאW N = 23 = 8
אא(4)אאW N = 24 = 16
אאאאאKאא)Bit(Wאאא
אאא20א)1((1)אאא21א(2)א22
(4)אKאאאאאאאאאא،אאא،אא
)itBignificant Seast L(אא)LSB(אאאMSB(K(אא) ) itBignificant Sost Mאאאא
א )ByteEWאא)Bit(אאאאאאאא،אאא0(א(
אא)1(אאFEאאאאאאKאאא
אK
א١٤٧ א א א
אא א
- ٦ -
א)Byte(אאאא
KאאאW 1 byte = 8 bits
١J٤אאאאא Decimal-to-Binary Conversion אאאא،אאא
)Sum of Weights Method(אאאא)2()Repeated Division–by–2 Method(אאא
אאאK١J٤J١אאאאאא
אא10)14(،אא142א،2אא)0 .(
אאאאאאKאאא)LSB(אאאא)MSB(אא،
W
14 ÷ 2 = 7 0 7 ÷ 2 = 3 1 3 ÷ 2 = 1 1 1 ÷ 2 = 0 1 1 1 1 0 (MSB) (LSB)
W (14)10 = (1110)2
F١J١WEאא(25)10אKאW
א
א١٤٧ א א א
אא א
- ٧ -
א
א
25 ÷ 2 = 12 1 (LSB) 12 ÷ 2 = 6 0 6 ÷ 2 = 3 0 3 ÷ 2 = 1 1 1 ÷ 2 = 0 1 (MSB)
אW (14)10 = (1110)2
F١J٢WEאא(87)10אKאW
87 ÷ 2 = 43 1 (LSB)
43 ÷ 2 = 21 1 21 ÷ 2 = 10 1 10 ÷ 2 = 5 0 5 ÷ 2 = 2 1 2 ÷ 2 = 1 0 1 ÷ 2 = 0 1 (MSB)
אW (87)10 = (1010111)2
١J٤J٢אאאאאאאאאאא
אא(2)Kאאא)Decimal Fractions (אאאא(2)K
אא)0.3125(אאאא0.3125(2)אאא،(2)אאא
(0)אאאאKאא)Carried Digits(אאאאאאאא
אKאאא)MSB(אאא)LSB(KאW
א١٤٧ א א א
אא א
- ٨ -
א
0.3125 × 2 = 0.625 0
0.625 × 2 = 1.25 1
0.25 × 2 = 0.5 0
0.5 × 2 = 1.00 1
(LSB) 1 0 1 0 (MSB)
F١J٣WEאא(39.25)10אKאWאאאאא(2)W
39 ÷ 2 = 19 1 (LSB) 19 ÷ 2 = 9 1 9 ÷ 2 = 4 1 4 ÷ 2 = 2 0 2 ÷ 2 = 1 0 1 ÷ 2 = 0 1 (MSB)
אW (39)10 = (100111)
אאאא(2)W
0.25 × 2 = 0.5 0
0.5 × 2 = 1.00 1
W (0.25)10 = (0.01)2
אאאW
א
א
אאאאאאא
FKE
א١٤٧ א א א
אא א
- ٩ -
(39.25)10 = (100111.01)2
١J٥אאאאא Binary-to-Decimal Conversion אאאאאאא(2)
אאאא16, 8, 4, 2, 1אKאאאאא)Bit(אא(1)
אאאאאאKאאאW
F١J٤WEאא1101001אKאW(1)אאאא
W26 25 24 23 22 21 20 : א
1 1 0 1 0 0 1 : אא = 1 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 0 × 22 + 0 × 21 + 1 × 20 = 64 + 32 + 8 + 1 = (105)10
אאאאאא ات Bits(( خان
אא)Binary Point (אאאאאאא)Decimal Point(אאאאאא
W ……24 23 22 21 20 • 2-1 2-2 2-3 2-4…….
אא
F١J٥WEאאא(0.1011)2אKאW
• 2-1 2-2 2-3 2-4 0 • 1 0 1 1 ∴(0.1011)2 = 1 × 2-1 + 1 × 2-3 + 1 × 2-4 = 0.5 + 0.125 + 0.0625 = (0.6875)10
א١٤٧ א א א
אא א
- ١٠ -
١J٦אאאאBinary Arithmetic אאאאאא
אאKאאאאאK١J٦J١אאBinary Addition
אאא،אאאא)Binary Digits(W
0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 carry FאE 1 ⇒ = 10
אאאאאא،אא1 + 1 = 10(2)אא،(1)אאאאא
אאאKאאאאW F١J٦WEאא011, 110KאWאאאאW
1 1 6 1 1 0 + 3 + 0 1 1 FE 9 1 0 0 1
F١J٧WEאאא011, 100KאW
4 1 0 0 + 3 0 1 1 FE 7 1 1 1
١J٦J٢אאBinary Subtraction אאW
١JאאאK٢JאאK
א١٤٧ א א א
אא א
- ١١ -
1
אא،אאKאאאFאEאאאאאא
אאאאאאW0 – 0 = 0 1 – 0 = 1 1 – 1 = 0 0 – 1 = 1 (1) א (1)א
אאאW• אאK Wאאאאאאאאא •
(0)(0)(1)(1)א(0)K (0)(1)א(1)K (1)(0)א(1)(0)אאFא
E(1)(1)(0)K אאאאאK
F١J٨WEאאא(101)אא(011)KאW
0 א1 0 1
א110–0 1 0
١J٧אאאאאOne's and Two's Complements of Binary Numbers
אאאאאאאKאאאאאאאאאK
אא)1()0()0()1(אאW
(1)אאא(10)א(1)
א(1)
א(1)א(0)
א١٤٧ א א א
אא א
- ١٢ -
אא1 0 1 1 0 0 1 1
אא0 1 0 0 1 1 0 0
אאאאWאאWאאKא(1) א
אאאאWאאZא1+ א
אאא10110011אKאא(1)אאאK
אא1 0 1 1 0 0 1 1
אא0 1 0 0 1 1 0 0
(1) 1 +
אא0 1 0 0 1 1 1 0
אאWאאאא)LSB(אא)0(אא
אאאאאאאאאאאFאאאאאא
אאאאאאE،אא(10101101)2אאW
אא1 0 1 0 1 1 0 1
אא0 1 0 1 0 0 1 1
١Jא٨אאאRepresentation of Signed Numbers
אאאאאאאאאאאאאאאאא
אאא،א(0)،א(1)אKאאאאאאא
אא
א١٤٧ א א א
אא א
- ١٣ -
אאאא)Sign Bit( אא)Magnitude .(
אאאאאאWאא
)Sign-Magnitude(אא) 1's Complement (אא)2's Complement.(١J٨J١אא) Sign-Magnitude System(
אא،אאאא)Bit(אאאאאאאאאKא
אאאאאאאאאאאKאא(+23)
אאאW
0 0 0 1 0 1 1 1
אא(-23) فإننا W1 1 1 0 0 1 0 0 1
אאא(+23) ، (–23)אK١J٨J٢אא )1's Complement System(
אאאאאאאאאאאאKאאאאאא
אKאא (–23)אאאW
0 0 0 1 0 1 1 1 )23+(א
23(א–(0 0 0 1 0 1 1 1
אאאאאאאאאK
א(Sign Bit) אא
(Magnitude Bits)
א١٤٧ א א א
אא א
- ١٤ -
١J٨J٣אא)2's Complement(אאאאאאאא
אאKאאאאאאKאא(-23)אאא(+23)W
0 0 0 1 0 1 1 1 )23+(א
23(א-(1 0 0 1 0 1 1 1אאאאאאאK
١J٩אאאאאאArithmetic Operations with Signed Numbers אאאא،
אאאאאאאא،אאF١J٦KEאא
אאאאאאאאאאאKאאאאאאאאW
F١J٩WEאאא00001110אא11111010אאאאKאWאW
14 – (– 6) = 14 + 6 = 20 אW
0 0 0 0 1 1 1 0 א(+14)
+ 0 0 0 0 0 1 1 0 אא (+6)
0 0 0 1 0 1 0 0 א(+20)
F١J١٠WEאאאאאאW (00001000)2 – (00000100)2
אWאW 8 – 4 = 8 + (-4) = 4
W
א١٤٧ א א א
אא א
- ١٥ -
א(Discard carry)
א(Discard carry)
0 0 0 0 1 0 0 0 א(+8)
+ 1 1 1 1 1 1 0 0 אא(-4)
1 0 0 0 0 0 1 0 0 א(+4)
F١J١١WEאאאאאאK
(11100111)2 – (00001001)2 אWאW
– 25 – (+9) = – 25 – 9 = -34 W
1 1 1 0 0 1 1 1 א(-25)
+ 1 1 1 1 0 1 1 1 אא(-9)
1 1 1 0 1 1 1 1 0 א (-34)
١J١٠אאאThe Octal Numbering System
אאאא(8)(8)(0,1,2,3,4,5,6,7)אאאאאא
אאאאאא،אאאאאאאאאאאK
١J١٠J١אאאאOctal-to-Decimal Conversion אאאאאאא(8)
(……83 82 81 80)،אאאאא)…... 512 64 8 1(،אKאאאאא
אאאKאאא(2275)8אאW
אא: 83 82 81 80
א5 7 2 2 : א ∴ (2275)8 = (2 × 83) + (2 × 82) + (7 × 81) + (5 × 80)
= (2 × 512) + (2 × 64) + (7 × 8) + (5 × 1) = 1024 + 128 + 56 + 5 = (1213)10
א١٤٧ א א א
אא א
- ١٦ -
א
א
١J١٠J٢אאאא Decimal–to–Octal Conversionאאאאאא
א(8)אאאאאאא،(8)(2)K
١J١٠J٢J١אאאאאאאא10)150(אאא150(8)
אא(8)א(0).אאאאאאK
אאאאאאא)LSD( igitDignificant Seast Lאאאאigit Dignificant Sost M)MSD(אאW
150 ÷ 8 = 18 6 (LSD) 18 ÷ 8 = 2 2 2 ÷ 8 = 0 2 (MSD)
אW (150)10 = (226)8
F١J١٢WEאא10)624(אאKאW
624 ÷ 8 = 78 0 (LSD)
78 ÷ 8 = 9 6 9 ÷ 8 = 1 1 1 ÷ 8 = 0 1 (MSD)
אW (624)10 = (611)8
١J١٠J٢J٢אאאאאאאאאאאאא
אא(8)Kאא)0.265(אאאא0.265(8)، אאא
א١٤٧ א א א
אא א
- ١٧ -
الحامل
א
الحامل
(8)אאא(0)אאאאKאא)Carried Digits (אאאאאK
אאא)LSD(אא)MSD(אW
0.265 × 8 = 2.12 2 (MSD) 0.12 × 8 = 0.96 0 0.96 × 8 = 7.68 7 0.68 × 8 = 5.44 5
0.44 × 8 = 3.52 3 0.52 × 8 = 4.16 4 (LSD)
אאאאאא(6)אאW (0.625)10 = (0.207534)8
F١J١٣WEאא10)44.5625(אאKאWאאאאא(8)K
44 ÷ 8 = 5 4 (LSD) 5 ÷ 8 = 0 5 (MSD)
אW (44)10 = (54)8
אאאא(8)W
0.5625 × 8 = 4.5 4 0.5 × 8 = 4.00 4
W (0.5625)10 = (0.44)8
אאאW (44.5625)10 = (54.44)8
א١٤٧ א א א
אא א
- ١٨ -
١J١٠J٣אאאאא Octal-to-Decimal Conversion אאאאאא(8)א
אאאא4096, 512, 64, 8, 1אKאאאאא)Digit(א
אאאאKאאK
F١J١٤WEאא(324)8אאKאW
אא: 82 81 80
אא: 3 2 4 ∴ (324)8 = (3 × 82) + (2 × 81) + (4 × 80)
= (3 × 64) + (2 × 8) + (4 × 1) = 192 + 16 + 4 = (212)10 אאאאאאאאא
אאא) Octal Point (אאאאאאW
……84 83 82 81 80 • 8-1 8-2 8-3 8-4……. אא
F١J١٥WEאא(567.14)8אאKאW
אא: 82 81 80 • 8-1 8-2
אא: 5 6 7 • 1 4 ∴ (567.14)8 = (5 × 82) + (6 × 81) + (7 × 80) + (1 × 8-1) + (4 × 8-2)
= (5 × 64) + (6 × 8) + (7 × 1) + (1 × 0.125) + (4 × 0.015625) = 320 + 480 + 7 + 0.125 + 0.0625 = (375.1875)10
א١٤٧ א א א
אא א
- ١٩ -
١J١٠J٤אאאאא Octal-to-Binary Conversion )Digit (אא
)3-bits(،אאאאאKאאF١J١KE
7 6 5 4 3 2 1 0 אא
111 110 101 100 011 010 001 000 אא F١J١EאאאK
אאאאK
F١J١٦WEאא(357)8אאKאW
(357)8 = 3 5 7 011 101 111
= (011101111)2 F١J١٧WEאא(1276.543)8אKאW
(1276.543)8 = 1 2 7 6 • 5 4 3
001 010 111 110 • 101 100 011
= (1010111110.101100011)2 אאאK
١J١٠J٥אאאאא Binary-to-Octal Conversion אאאאאאאא
אKאא–Jאאאא
אאאאאאא
א١٤٧ א א א
אא א
- ٢٠ -
אאאאאאK
F١J١٨WEאא(1011001011100.00101)2אאKאW
001 011 001 011 100 • 001 010
1 3 1 3 4 • 1 2 אאאאאא
W (1011001011100.00101)2 = (13134.12)8
١J١٠J٦אאאא Arithmetic Operations in Octal System אאאאK
١J١٠J٦J١אאOctal Addition אאאאא–א)0,9(א
(9)אאא،(9)א(10)אאאאאאKאאא
אאא0,1(א(אא(10)אאאאאאKא
אאאאאאאאאאא(7)אאא–אאאא(7)א
(10)אאאאאא،א)11, 12, 13, 14, 15, 16, 17(אאא) 20,21, 22, ...... , 27(אאא)30, 31, ..... , 37 (אK
א F١J٢Eאאאאאאאאאאאאא
אאאאאKאאאW
א١٤٧ א א א
אא א
- ٢١ -
• אאאאאאא(7)K
• אאא(7)אא(2)אא،(7)אאא(8)א(7)א
א(10)אא(2)אאאאאFאאאא
אאאKE
+ 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 6 7 1 1 2 3 4 5 6 7 102 2 3 4 5 6 7 10113 3 4 5 6 7 1011124 4 5 6 7 101112135 5 6 7 10111213146 6 7 1011121314157 7 10111213141516
F١J٢EאאאK
F١J١٩WEאאא (38)8،(42)8KאWאאW
34 + 42 76
∴(34)8 + (42)8 = (76)8
אא(4,2)(3,4)(7)אK
א١٤٧ א א א
אא א
- ٢٢ -
F١J٢٠WEאאא(56)8،(63)8KאW
5 6 + 6 3 1 4 1
אאא(7)(2)אא)Carry(אאK
١J١٠J٦J٢אאאSubtraction in Octal System אאאW
• אאאאאK• אאא(1)אא–אאא
(8)אאאאאאאאאK
F١J٢١WEאאW (657)8 – (346)8
אWאW 6 5 7 א
– 3 4 6 א 3 1 1
∴(657)8 – (346)8 = (311)8 אאא
אאKF١J٢٢WEאאW(732)8 – (634)8 אW
7 3 2 א
– 6 3 4 א 0 7 6
∴(732)8 – (634)8 = (76)8
6 2 1
א١٤٧ א א א
אא א
- ٢٣ -
אא(4)(2)אא(1)אא،אאאאאא
אאא(3)(2)אאK١J١١אאאא Hexadecimal Numbering System
אאאאא(16))16(א) 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F(א)A,B,C,D,E,F(אא(10, 11, 12, 13, 14, 15)אK١J١١J١אאאאHexadecimal–to–Decimal Conversion
אאאאאאא16א(……163 162 161 160)אאאא )... 4096 256 16 1(
אאא16)522.39(W
אא: 162 161 160 • 16-1 16-2
אא: 5 2 2 • 3 9 ∴ (522.39)16 = (5 × 162) + (2 × 161) + (2 × 160) + (3 × 16-1) + (9 × 16-2)
= (5 × 256) + (2 × 16) + (2 × 1) + (3 × 0.0625) + (9 × 0.0039062) = 1280 + 32 + 2 + 0.1875 + 0.0351558 = (1314.222655)10
אאאאאאKאאא(16)אאאK
١J١١J٢אאאאDecimal-to-Hexadecimal Conversion אאאאאאאא(16)
אאאאאאאאאאאא(16)(8)(2).
١J١١J٢J١אאאאאאאאא10)97(אאא97(16)
אא(16)א(0)Kאאאאא
א١٤٧ א א א
אא א
- ٢٤ -
א
א
الحامل
אאK،אאאאאא)LSD(אא)MSD(אאW
97 ÷ 16 = 6 1 (LSD) 6 ÷ 16 = 0 6 (MSD)
אW (97)10 = (61)16
F١J٢٣WEאא(314)10אאאKאW
314 ÷ 16 = 19 A (LSD)
19 ÷ 16 = 1 3 1 ÷ 16 = 0 1 (MSD)
אW (314)10 = (13A)16
١J١١J٢J٢אאאאאאאאאאאאא
אא(16)אKאא(0.78125)10אאאאא(16)אא
(16)אאאאאא(0)אאאאאאKאאאאאאKאאא(LSD)אאא(MSD)
אW
0.78125 × 16 = 12.5 C 0.5 × 16 = 8.00 8
W ∴(0.78125)10 = (0.C8)16
א١٤٧ א א א
אא א
- ٢٥ -
א
א
F١J٢٤WEאא(329.52)10אאKאWאאאאא16W
329 ÷ 16 = 20 9 (LSD) 20 ÷ 16 = 1 4 1 ÷ 16 = 0 1 (MSD)
אW ∴(329)10 = (149)16
אא(16)אאW
0.52 × 16 = 8.32 8 (MSD) 0.32 × 16 = 5.12 5 0.12 × 16 = 1.92 1 0.92 × 16 = 14.72 E 0.72 × 16 = 11.52 B 0.52 × 16 = 8.32 8 (LSD)
אאאאא(6)אW
(0.52)10 = (0.851EB8)16 אאאW
(329.52)10 = (149.851EB8)16
١J١١J٣אאאא Hexadecimal-to-Decimal Conversion
אאאאאאא(16)אKאאאאא
אאKאאW F١J٢٥WEאאא(F9B)16אאKאW
אא: 162 161 160
אא: F 9 B
א١٤٧ א א א
אא א
- ٢٦ -
∴ (F9B)16 = (F × 162) + (9 × 161) + (B × 160) = (15 × 256) + (9 × 16) + (11 × 1) = 3840 + 144 + 11 = (3995)10 אאאאאאאאאאא
אאאאאW
……163 162 161 160 • 16-1 16-2 16-3 ……. אא
F١J٢٦WEאאא(A15.C3)16אKאW
אא: 162 161 160 • 16-1 16-2
אא : A 1 5 • C 3 ∴ (A15.C3)16 = (A × 162) + (1 × 161) + (5 × 160) + (C × 16-1) + (3 × 16-2)
= (10 × 256) + (1 × 16) + (5 × 1) + (12 × 0.0625) + (3 × 0.0039062) = 2560 + 16 + 5 + 0.75 + 0.0117186 = (2581.7617)10
١J١١J٤אאאאאHexadecimal-to-Binary Conversion
אאאא(0,1,2,……,9,A,B,C,D,E,F)אאא(A,B,C,D,E,F)אאאא
(10,11,12,13,14,15)Kאאאאאאאא،אא(4-bits)
אאF١J٣WE F١J٢٧WEא(3A5)16אKאW
(3A5)16 = 3 A 5
0011 1010 0101 = (001110100101)2
א١٤٧ א א א
אא א
- ٢٧ -
אאאאאאא0 0000 0 1 0001 1 2 0010 2 3 0011 3 4 0100 4 5 0101 5 6 0110 6 7 0111 7 8 1000 8 9 1001 9 10 1010 A 11 1011 B 12 1100 C 13 1101 D 14 1110 E 15 1111 F
F١J٣EאאאK
F١J٢٨WEא(B35.D1)16אאKאW
(B35.D1)16 = B 3 5 • D 1
1011 0011 0101 • 1101 0001
= (101100110101.11010001)2
١J١١J٥אאאאאBinary-to-Hexadecimal Conversion
אאאאאאאאאאאאאאאאא
Kאאאאאאאאא
אאאאK
א١٤٧ א א א
אא א
- ٢٨ -
F١J٢٩WEאא(110111101.101001)2אאKאW
0001 1011 1101 • 1010 0100
1 B D • A 4 אאאK
∴(110111101.101001)2 = (1BD.A4)16 F١J٣٠WEאא(11010010011.011001)2אאאKאW
0001 1010 1011 • 0110 1000
1 A B • 6 8
∴(11010010011.011001)2 = (1AB.68)16
١J١١J٦אאאאאHexadecimal-to-Octal Conversion
אאאאאאאאאאאאאאאא
אאאWF١J٣١WEא(AB3E.87D)16אאKאWאאאאW
(AB3E.87D)16 = (1010101100111110.100001111101)2 אאאאא
W
001 010 101 001 111 110 • 100 001 111 101
1 2 5 4 7 6 • 4 1 7 5 אאK
∴(AB3E.87D)16 = (125476.4175)8
א١٤٧ א א א
אא א
- ٢٩ -
١J١١J٧אאאאאOctal-to-Hexadecimal Conversion
אאאא،א
،אאאאאאאאW
F١J٣٢WEאא(25.342)8אאאKאWאאW
∴(25.342)8 = (010101.011100010)2
אאאאאW 0001 0101 • 0111 0001
1 2 • 7 1
אאאאאאK
∴(25.342)8 = (12.71)16
١J١١J٨אאאאאArithmetic Operations in Hexadecimal System
אאאאK١J١١J٨J١אאאאHexadecimal Addition
אאאא(0,F)אאאא(F)(10)אא،(10)אאאאאאא
אאאאאאאKאאאאאאאא
א16(9)אא(A)16אא(9)16(B)16א(F)16K
אא(F)1616(10)אאאאאאאא(F)1616(11)אאאא
Kאאאאא
א١٤٧ א א א
אא א
- ٣٠ -
111
אF١J٤Eא،אאאאאאאאאאאאא
אאאאאK
+ 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 1 1 2 3 4 5 6 7 8 9 A B C D E F 10 2 2 3 4 5 6 7 8 9 A B C D E F 10 11 3 3 4 5 6 7 8 9 A B C D E F 10 11 12 4 4 5 6 7 8 9 A B C D E F 10 11 12 13 5 5 6 7 8 9 A B C D E F 10 11 12 13 14 6 6 7 8 9 A B C D E F 10 11 12 13 14 15 7 7 8 9 A B C D E F 10 11 12 13 14 15 16 8 8 9 A B C D E F 10 11 12 13 14 15 16 17 9 9 A B C D E F 10 11 12 13 14 15 16 17 18 A A B C D E F 10 11 12 13 14 15 16 17 18 19 B B C D E F 10 11 12 13 14 15 16 17 18 19 1A C C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B D D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C E E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D F F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E
F١J٤EאאאאK F١J٣٣WEאאW
(35AB2)16 + (1A675)16
אWאאאאאאK 3 5 A B 2 + 1 A 6 7 5 5 0 1 2 7 ∴(35AB2)16 + (1A675)16 = (50127)16
١J١١J٨J٢אאאאHexadecimal Subtraction
אאאאאW
א١٤٧ א א א
אא א
- ٣١ -
• אאאאאאאאאאאאK
• אאא(1)אאאאאאאאאאאאא
אאW F١J٣٤WEאאW
(F2ABD)16 – (EF4CE)16 אW
F 2 A B D – E F 4 C E 3 5 E D
אאאK
1 1A91E
א١٤٧ א א א
אא א
- ٣٢ -
١EאאאאאאWa) 64 b) 112 c) 257 d) 27.26 e) 77.0625 f) 47.875 g) 33.125
٢EאאאאאאWa) 11011 b) 1110101 c) 111111 d) 1110.11 e) 10101.1101 f) 1100001.11011
٣EאאאאWa) 100 + 111 b) 1110.11 + 11.10 c) 1111 + 1101 d) 1001.101 + 1101.11
٤EאאאאאWa) 1101 – 0100 b) 1001 – 0111 c) 11010 – 10111 d) 1100 – 1001
٥EאאאאאאWa) 00110101 b) 11100100 c) 00010101
٦EאאאאאאWa) 11110110 b) 01011101 c) 00110011
٧Eאאאאאאאאאאאאא(8-bits) W
a) +28 b) – 83 c) +99 d) – 120
٨Eאאאאאאאאאאאא(8-bits) W
a) +14 b) – 63 c) +107 d) – 122
א١٤٧ א א א
אא א
- ٣٣ -
٩EאאF٨EאאאאK
١٠EאאאאאאאאאאאWa) 101110001 b) 01100100 c) 10110011
١١EאאאאאאאאאאאWa) 10011101 b) 01100110 c) 10101101
١٢EאאאאאאאאאאאWa) 10101011 b) 000111101 c) 10111011
١٤EאאאאאW
a) 00010110 – 00110011 b) 01110000 – 10101111 c) 10001100 – 00111001 d) 11011001 – 11100111
١٥EאאאאאאאWa) 50 b) 100 c) 6391 d) 77.375 e) 120.515625 f) 144.5625 g) 915.141
١٦EאאאאאאאWa) 42 b) 254 c) 1057 d) 37.5 e) 96.11 f) 115.3 g) 14367.12
١٧EאאאאאאאWa) 72 b) 113 c) 16.3 d) 37.6 e) 122.775 f) 417.632 g) 276.621
١٨EאאאאאאאWa) 110101.1101 b) 11110100.110101 c) 110110111.10101 d) 10001001011.1001 e) 1010111.11101
١٩EאאאאWa) (15)8 + (17)8 b) (44)8 + (66)8 c) (123)8 + (321)8 d) (272)8 + (456)8
א١٤٧ א א א
אא א
- ٣٤ -
٢٠EאאאאWa) (32)8 – (25)8 b) (147)8 – (74)8 c) (315)8 – (222)8 d) (437)8 – (340)8
٢١EאאאאאאאאWa) 14 b) 80 c) 560 d) 3000 e) 62500 f) 204.125 g) 255.875 h) 631.25
٢٢EאאאאאאאWa) 9F b) D52 c) 67F d) ABCD e) F.4 f) B3.E g) 1111.1 h) 888.8
٢٣EאאאאאאאאאWa) 8 b) 1C c) A64 d) 1F.C e) 239.4
٢٤EאאאאאאאאWa) 1001.1111 b) 10000.1 c) 110101.11001 d) 10100111.111011 e) 1000000.000111 f) 1111100.1000011
٢٥EאאאאאאWa) 13A b) 25E6 c) 3016 d) B4.C e) 78.D3 f) 2659.F41
٢٦EאאאאאאWa) 37 b) 725 c) 2476.2 d) 1117.16 e) 1600.524 f) 3000.6125
٢٧EאאאאWa) (41)16 + (36)16 b) (C8)16 + (3A)16 c) (9B)16 + (65)16 d) (11D)16 + (2E1)16 f) (77CB5)16 + (A5F72)16 g) (13EFD)16 + (21BB3)16
- ١ -
אאאאאאאא
אא
אאאã¹]<gè…‚jÖ]æ<ËÖ]<Üé×Ãj×Ö<íÚ^ÃÖ]<퉉ö¹]
אאאא
א
אא
א
٢
- ١ -
א١٤٧ א א א
אאאא א
- ٣٥ -
אאא
אאW• אאאאאK • אאאאאK • אאאאK • אאאאאK • אאאאאK • אאאאK • אאאאאK • אאאאאאאK
א١٤٧ א א א
אאאא א
- ٣٦ -
٢J١ Introduction
אאאJאJאJאJ،אאאאאאא
אאאא،אאאאאאאאאא،אא
אאאK،אאאאא?אא?אאאאאא
אאKאאאאאאאא
אאANDא،ORא،NOTא(INVERTER)Kא،אאאאאאאאא
אאאאK٢J٢אאLogic Signal Levels
אאאאאאאא،אאKאאאאא
،،،אאאא
אא،אאאאJאא(HIGH)א(1)א،א(LOW)
(0)אאא،א(1)אא(TRUE)،אא(0)אאא
(FALSE)Kא،א(Positive Logic)،אא(Negative Logic)Kאאאאא(1)א
אא(0)אא،אא،א(0)אא(1)אאאאK
א١٤٧ א א א
אאאא א
- ٣٧ -
٢J٣א ANDAND GateאאANDאאאאאאאא
(Logic Functions)KאאANDאא،אא(Logical Multiplication)،אאאא
אאאא F٢J١E،אA, Bאאאא(Two Binary Variables)(0)א
א(Open)(1)אא(Closed)K
F٢J١EאאANDאאK
א"L"אאא(1)א(ON)(0)א(OFF)Kאא
،،אF٢J١Eאאא(L)אKאא(L)
אאאא،א(Truth Table)KL B A
F٢J١Eאא F٢J١KE
Voltage Source
(A) (L) (B)
א١٤٧ א א א
אאאא א
- ٣٨ -
אF٢J٢Eאאא(Standard)אANDא،A, BאYאא،ANDKאF٢J٢EאאANDK
א אYBA0000100011 1 1
F٢J٢EאאANDKF٢J٢EאאANDK
א(bits)،א(1)אאA, B(1)،אאAND،אא
א(1)א(1)KאאJאאאאW
n2N = W Nאא
nאאKW
אא42N 2 ==אא82N 3 ==אא162N 4 ==
F٢J١EW• אאאANDK• אאAND؟אWאAND،אאF٢J٣Eא
אאK
YBA
א١٤٧ א א א
אאאא א
- ٣٩ -
אא
Y C BA0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 010 1 0 1 0 0 1 1 11 1 1
F٢J٣EאאANDK
•אאאW 3222N 5n ===
אא(Boolean Algebra)אאאאאא،א(Boolean Expression)אא
KאאאANDאW BAY •=
אWאYA AND BF•ANDEא،
אאW Y = AB
אYA AND BKאאא(Pulses)אא(HIGH)א(LOW)Kא
אANDאא،אאאK
،F٢J٣EאA, B(1)אאt1אאYא(1)،אאt2א،A
א١٤٧ א א א
אאאא א
- ٤٠ -
(0)אBאY(0)،אאאאאKאאאאאא
(Timing Diagram)K
F٢J٣EאאאANDK٢J٤ א OROR Gate
אאORאאאאאאאאKאאOR،אאאא
(Logical Addition)אאאאאאא، F٢J٤EKאאANDאA, B
(0)א(Open)(1)א(Closed)K
F٢J٤EאאORאאKF٢J٤Eאא،אאא
אא(L)אK
Voltage Source (B)
(A)
Y B A
t7t6t5t4t3t2t1
Y
A
B
א١٤٧ א א א
אאאא א
- ٤١ -
L B A
F٢J٤EאאF٢J٤KE
אF٢J٥EאאאאORא،A, BאYKאF٢J٥EאאORK
א א
YBA0 00 1 1 0 10 1 1 1 1
F٢J٥EאאORKF٢J٥EאאORK
אF٢J٥Eא(1)אא(1)،א(0)א
(0)אKאאאORאW Y = A + B
אWאYA OR B+)OR(KאאOR،אא
אANDאאאאK
F٢J٦EאA, B(1)אאt1אאYא(1)،אאt2א،A
(0)אBאY(1)،אאאאאK
YAB
א١٤٧ א א א
אאאא א
- ٤٢ -
F٢J٦EאאאORK
٢J٥א NOT FאE NOT Gate (INVERTER)אאNOTא(Inversion)א
(Complementation)Kא،אאא(1)א(0)،א(0)(1)K
אאNOTאאאKF٢J٧Eא،אאאאאF٢J٦EאאאK
א א
YA1 0 0 1
F٢J٧EאאNOTKF٢J٦EאאNOTאK
א،אאאאאW
Y = A אאWאYnot AאAbarא
،אאYA barFAEK
٢J٦א NAND NAND Gate
YAB
Y
t7t6t5t4t3t2t1
A
B
Y A
א١٤٧ א א א
אאאא א
- ٤٣ -
(NAND)א(NOT AND)ANDאא،אאאאאANDF٢J
٨E،אאאאאאANDאאאאאKF٢J٧EאאNANDK
א א
YBA1 00 1 1 0 1 0 1 0 1 1
F٢J٨EאאNANDKF٢J٧EאאNANDK
אא(0)אאא(1)א،א (1)אאא(0)
אאא،אANDKאאNANDאאאאאאאאא،א
אNOT, OR, AND،אא،אאNANDאW
Y = AB אאNAND،אא
אאNAND(0)א(1)KF٢J٩EאA, B(1)אאt1א
אY(0)א،אאt2א،A(0)אB(1)אY(1)،אאא
אאK
YA B
א١٤٧ א א א
אאאא א
- ٤٤ -
Y B
A
F٢J٩EאאאNANDK
٢J٧א NOR NOR Gate (NOR)א(NOT OR)ORאא،
אאא(NOT gate)אאORF٢J١٠E،אאאאNORKאאNOR
F٢J٨KE
א אY BA1 00 0 1 0 0 0 1 0 1 1
F٢J١٠EאאNORKF٢J٨EאאNORK
אא(Y)(0)אאא (1)אא،(1)אא
(0)אKאאNORאאאNANDאאאאאא
א،אNOT, OR, AND،KאאאNORW
Y = BA +
Y t7t6t5t4t3t2t1
A
B
Y A B
א١٤٧ א א א
אאאא א
- ٤٥ -
Y A B
F٢J١١EאNORאA, Bא،אאאNORאא(Y)אK
F٢J١١EאאאNORK٢J٨א OR אFאEExclusive-OR Gate
אאORאא??XOR-gate،F٢J١٢EאאאKאאXORאאא
אK
א אYBA0 00 1 1 0 1 0 1 0 1 1
F٢J١٢EאאXORKF٢J٩EאאXORKאאXOR(9-2)،אא(Y)
(1)אאA, B،(1)א(0)،א(0)אK
אאXORאאORאאאA = B = 1 אא،XOR(1)
(1)א(1)،אאKאאאאאא
Y
t5t4t3t2t1
A
B
Y
B
A
א١٤٧ א א א
אאאא א
- ٤٦ -
אאאאאאW Y = BABA +
אאאאW Y = A ⊕ B
א⊕ABKאאאאXOR
אאאאAND, OR, NOTאא،F٢J١٣EאאאאאXORאK
F٢J١٣EאאXORאAND, OR, NOTK
F٢J١٤EאאXORאאאא،א
אK
F٢J١٤EאאאXORK
t8t7t6t5t4t3t2t1
A
B
Y
Y A B
Y
AB
א١٤٧ א א א
אאאא א
- ٤٧ -
Y AB
٢J٩א NOR אFאEExclusive-NOR Gate אאNORאXNOR-gateא،א
אאאXOR،F٢J١٥EאאאKאאXNOR F٢J١٠Eאא،(Y)
(1)אאA, BA = B = 0A = B = 1(0)א(1)א(0)،א(1)א،אאא
אאאאK
א אYBA1 00 0 1 0 0 0 1 1 1 1
F٢J١٥EאאXNORKF٢J١٠EאאXNORKאאאאאאW
Y = BAAB+ אאאW
Y = A B אאKאאאאXNORאא
אאAND, OR, NOTאא،F٢J١٦EאאאאאXNORאK
F٢J١٦EאאXNORאAND, OR, NOTK
Y
AB
א١٤٧ א א א
אאאא א
- ٤٨ -
F٢J١٧EאXNORאA, B،אאאXNORאא(Y)K
F٢J١٧EאאאXNORK٢J١٠אאאRules of Boolean Algebra
F٢J١١EאאאאאאאאK
2. A + 1 = 11. A + 0 = A4. A • 1 = A3. A • 0 = 06. A + A = 1 5. A + A = A8. A • A = 0 7. A • A = A10. A + AB = A9. A = A
F٢J١١EאאאאKאאאאאאא
אK(1)א: A + 0 = Aאאא
אORא(0)،אאAא،(1)(0)KאA=1(1)אאAKאA=0(0)אAK
אOR(0)אאא(A + 0 = A)K(2)א:A + 1 = 1אאאאORא(1)א،אAא،(1)א(0)K(1)אאORא
Y
t8t7t6t5t4t3t2t1
A
B
Y
AB
א١٤٧ א א א
אאאא א
- ٤٩ -
(1)אאאאאKאOR(1)א(1) א(A + 1 = 1)K(3)א:A • 0 = 0אאאאANDא(0)
،אאA،א(0)אאאאאאKאAND(0)א(0)א
(A • 0 = 0)K(4)א:A • 1 = AאאאאANDא(1)
א،אA،אא(A)،אאA=0אאAND(0)،אאA=1אאAND(1)אא
(1)KאAND(1)אאא(A • 1 = A)K
(5)א:A + A = AאאאאORאA،אאאKאאA = 00 + 0 = 0אא،
A = 1א1 + 1 = 1K(6)א:1AA =+אWאAא
ORאAאאאאא(1)אKאA=011000 =+=+KאA = 110111 =+=+K
(7)א:A • A = AאאAאאANDאאאKאאA = 00 • 0 = 0אא،A = 1א1 • 1 = 1،
אאאANDאAK(8)א:0AA =•אAאANDאAאא
אאא(0)א،אאאAA(0)،א(0)אANDאא(0)K
(9)א: AA =אאאאKאאA = 0(1)،א(1)(0)
אאK
א١٤٧ א א א
אאאא א
- ٥٠ -
(10)א:אאא(2)א(4)W A + AB = A (1 + B) = A (1) = A
٢J١١אאאThe Boolean Expression for a Logic Circuit،אאאאא
אאאאאKאאא،אF٢J١٨EKאאאאאW
١KאאאANDאאBA, BAK٢KאאאANDאא,C ACAK٣KאאאORאאCA ,BACABA +K
אאאW CABAY +=
F٢J١٨EאאאאK
F٢J٢EWאאאאאאF٢J١٩EKאW
F٢J١٩EאאאF٢J٢EאאאK
)BA(D +
CB +
CB +
D
C
Y
AB
BA
A
B
CA
Y
AB
C
א١٤٧ א א א
אאאא א
- ٥١ -
אאאאאW )CB()BA(DY +++=
٢J١٢אאאאImplementation of a Logic Circuit Using a Boolean Expression
אאאאאאKאאאאW
)EFDC(ABY +=
אאאאאA, B)EFDC( +
אANDא،)EFDC( +D,CאAND،E,FאANDאא،ANDאORK
אאW
)EF DC( B AY +=
אאאאא)EFDC( +؛
אאאאאEF ,DCאא؛Dאאא،K
אאאאאא)EFDC(AB +W١KאNOTאDK٢KאANDאEF ,DCK٣KאORאא)EFDC( +K٤KאANDאאYK
אאאאאאא F٢J٢٠KE
AND
AND
OR
NOT
א١٤٧ א א א
אאאא א
- ٥٢ -
F٢J٢٠EאאאאEF)DAB(C +K
٢J١٣אאImplementation of a Logic Circuit via a Truth Table
אאאאאאאאאא،אא
אKF٢J١٢Eאא،אאאאאאאKאאאאW
١K אאאאY = 1אא،אאY = 1אA = 0, B = 1, C = 0،
אאCBAאא(1)،א(0)،(1)אאאאא
אאCABK
אאY C BA0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 0 0 010 1 0 1 1 0 1 1 0 1 1 1
F٢J١٢EאאאK
AB
DC
EF
Y
א١٤٧ א א א
אאאא א
- ٥٣ -
٢K אאאאאY = 1אORW
CABCBAY +=
אאאאא CBAאאאC,B,AאANDאאאא،CAB
אאאC,B,AאANDאאאא،ORאאאYK
אאאאאאאWאNOTאC,Aא؛ANDאאCBA،CABא،OR
אאאCABCBA +אאאאאאא، F٢J٢١EK
F٢J٢١EאאאאCABCBA +K F٢J٣EWאאאאאאא F٢J١٣KE
אאY C BA 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 011 1 0 1 0 0 1 1 0 1 1 1
F٢J١٣EאאאאאK
C Y
A
B
א١٤٧ א א א
אאאא א
- ٥٤ -
אWאאאאאאאY = 1 FאאEאORW
CBABCACBAY ++=
אאא F٢J٢٢EK
F٢J٢٢EאאאאCBABCACBA ++K
٢J١٤אאאConverting a Boolean Expression to a Truth Table
אאאאאא(1or 0)K،אא(22 = 4)،
،אא(23 = 8)،אKאאא،אאא
א(1)אא(Y)،אא(0)אא،אאK
F٢J٤WEאאאW ABCCABCBACBAY +++=
אWא(A, B, C)א،אאא
אאאאא F٢J١٤EKאאאאאאW
111ABC ,110CAB ,010CBA ,000CBA ====
BA
CY
א١٤٧ א א א
אאאא א
- ٥٥ -
אא(1)א(Y)،אא(0)אא(Y)K
אא
Y C BA 1 0 0 00 1 0 0 1 0 1 0 0 1 1 0 0 0 010 1 0 1 1 0 1 1 1 1 1 1
F٢J١٤EאאABCCABCBACBAY +++=K
٢J١٥אאאאאאSimplification of Boolean Expressions Using Boolean algebra
אאאאאאאFאאאE،א،אאא
א،א،אאאאאאK
F٢J٥WEאאאאאאאאW )CA(B)CA(AABY ++++=
אWאאאאאאאW
BCABACAAABY ++++=
אAAAFאא7אאאEאאW BCABACAABY ++++=
א5A + A = A،AB + AB = ABאא،W
BCACAABY +++=
א١٤٧ א א א
אאאא א
- ٥٦ -
אAאאאאW
BC)C1B(AY +++= א2A + 1 = 1،W
Y = A • 1 + BC אא4A • 1 = A،W
Y = A + BC אאאK
אאאאאאאאאאאאאאאא،א
אאKF٢J٢٣Eאאאא
אאFאFEEאאא،אאFאFEKE
F٢J٢٣EאאאF٢J٥EK
אאאאא،A, B, C،אאאK
F٢J٦WEאאאאאאאאK
ABCBCACBACBAY +++= אW،אאאא،אאאW
)ABCBCA()CBACBA(Y +++= )AA(BC)CC(BA +++=
A
BC
FE
Y
Y
AB
FEC
א١٤٧ א א א
אאאא א
- ٥٧ -
א6W 1BC1BAY •+•=
א4אאאW
BCBAY +=
F٢J٢٤EאאאאK
F٢J٢٤EאאאF٢J٦EK
B
A
C
Y
C
Y
A
B
FE FE
א١٤٧ א א א
אאאא א
- ٥٨ -
١EאאאXאANDאאA,B،אJ١Kאא
J١
٢EאאאXאORאאA,B،אאאJ١K
٣EאאאXאNANDאאA,B،א
אאJ٢K
J٢
X
A
B
A
B
X
א١٤٧ א א א
אאאא א
- ٥٩ -
٤EאאאXאNORאאA,Bאא،אאJ٣K
J٣
٥EאאאXאXORאאA,Bאא،
אאJ٣K
٦EאאאXאXNORאאA,Bאא،אאJ٣K
٧EאאאאאJ٤K
J٤
A
B
X
C Y
AB
א١٤٧ א א א
אאאא א
- ٦٠ -
٨EאאאאאאאאWa) BABA + b)
c) d)
٩EאאאאאאK
אאY C BA 0 0 0 01 1 0 0 0 0 1 0 1 1 1 0 0 0 011 1 0 1 0 01 1 1 1 1 1
١٠EאאאאאW
a) b) c) d)
١١EאאאאאאאW
a) b) b) d)
BCAABAB ++)DC(BA + )]CB(DC[BA +++
C)BA( + )CB)(BA( ++)BAAC(A + )BAA(A +
)CA)(BA( ++ EDCBABCDACBABA +++)CABAB)(AA( ++ ABC)BA(AB +++
אאאאאאאאאא
אא
אאאã¹]<gè…‚jÖ]æ<ËÖ]<Üé×Ãj×Ö<íÚ^ÃÖ]<퉉ö¹]
אאאא
א
א
א
אא
٣
א١٤٧ א א א
אאאאא א
- ٦١ -
אאא
אאW
• K • אאאאNANDאאNORK • אאאאאאאNANDNORK • אאאאאK • אאאאK
א١٤٧ א א א
אאאאא א
- ٦٢ -
٣J١Introductionא،אאאאאא
אאאאאאאKאאאא،،אאא
אאאאאK،אאאאא0(א1(אאאK
אאאאאאאאאאNANDאאNORאאאאאאK
אאאא)Karnaugh-Map( אא–K )K–map(K
אאאאאאאאאאאK
٢J٣Demorgan's Theorems
אאא،אאאANDאORKאא
)bars(אאאא،אW
אW אWBABA +=•
אאORאAND
F٣J١EאאNORאאאאANDאאאאאאאאK
אאאF٣J١EKאאאאאאאANDא)negative AND(K
BABA •=+
א١٤٧ א א א
אאאאא א
- ٦٣ -
F٣J١EאORANDK
אאB A
1 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 F٣J١EאאK
אאANDאORF٣J٢EאאNANDאאאאORא
אFאאאאאאEא،אאאF٣J٢KEאאאאאאOR
א)negative OR(K
F٣J٢EאANDORK
אאB A
1 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 F٣J٢EאאK
BA + BA •
BA + BABA
B
A
ABA B
BA +A
B≡
BA • BA +
א١٤٧ א א א
אאאאא א
- ٦٤ -
אאאאKאאאאK
F٣J١WEאאאW
) C B A( )C B (A Y ++•++=
אW
CBA B CA C B A C B A
)C B A ( ) C B A (
)C B A () C B (A Y
+=+=
+++++=
++•++=
F٣J٢WE אאאW
אW
)DC(BA
)DC)(B.A(
CD).BA(
CD)BA(Y
+=
+=
+=
++=
٣J٣אאאאNOR , NAND
The Universal Property of NAND and NOR Gates אאאאאאאאANDא،
ORאא،KאאאNANDאNORא)Universal Gates (Kאאא
אNANDאאאAND،NORKאNORאאאNOR
אאAND،ORNANDK
CD)BA(Y ++=
א١٤٧ א א א
אאאאא א
- ٦٥ -
٣J٣J١אאNANDNAND gate as a Universal Logic Element אאNANDאא،אאAND،
OR،NORKאאאNANDאא٣אJ٣FEאNANDאK
AND אאNAND٣J٣FKEאאORא אNAND٣J٣FKEאאאNOR
٣J٣FKE
F٣J٣EאאאNANDK
A AAA ≡FE
ABBAABAB =ABA
B ≡FE
AA
≡BB
BAB.A += A + B A
B
FE
BA +
AA
≡BB
BAB.A +=
BA +A
B
FE
א١٤٧ א א א
אאאאא א
- ٦٦ -
٣J٣J٢אאNORNOR Gate as a Universal Logic Element אNAND ،אאNOR אאאAND،OR،אNANDKF٣J٤EאאNORא
NOTאORאאNANDK
F٣J٤EאאאNORK
AA ≡AA
B.ABA =+
AA
BB
≡ ABBA
B.ABA =+
A
AA
BB
≡ ABA B
≡ A + B A
BBABA +=+A
B
BA +
FE
FE
FE
FE
א١٤٧ א א א
אאאאא א
- ٦٧ -
٣J٤אאאאאאאNAND،NOR Design of Combinational Logic Circuits using NAND and NOR Gates
אאאNANDא،NORאאאאאאאNANDאאORא)Negative-OR(،
אאNORאאANDא)Negative - AND(KאאORANDאאאא) Logic diagram (אK
٣J٤J١אאאNANDNAND Logic א،NANDאNAND אOR א،א
אW
B ABA +=•
אאאאאF٣J٥KE
F٣J٥EאאאNANDK
אא)Y(אאאאאאW
)CD)(AB( Y = אW
CD AB Y += אאא)bars(W
CD AB Y += א)Y(،AB+CD א،AND
א.ORאאא)Y(אאNANDא
NAND Negative-OR
Y = AB + CD
ABA B
CD
C D
א١٤٧ א א א
אאאאא א
- ٦٨ -
F٣J٥EאANDאNANDאאORKאא)Y(א٣J٦FEאאאאNAND
אאOR אKאאא٣J٦FE،אאF٥-٣Eאא٣J٦FE،
W(AND-AND-OR)(NAND-NAND-NAND)
F٣J٧EאאNANDאאא
אאאORJאK
א(Y)אF٣J٧WE
F)ED(C)BA(F)ED(C)BA(
]F)ED[(]C)BA[(
]F)DE[(]C)AB[(F
+++=
+++=
+•+=
•=
Y
FDE
CABABA
B C
DEDE
F
F٣J٧EאאאאאאORJאK
Y = AB + CDAB
A
B
CD
C
D FE
≡ Y = AB + CD
A
B
C
DFE
F٣J٦EAND-AND-ORאאF٣J٥KE
א١٤٧ א א א
אאאאא א
- ٦٩ -
א אORJא א אNAND א אאF٣J٨Eא،(Y)אאאK
F٣J٣WEאאאאNANDW
אWאאF٣J٩KE
٣J٤J٢אאאNORNOR Logic אאNORאNORאANDJאא
אW
B ABA •=+
אאאאF٣J١٠KE
NOR Negative-AND
EDABCY)b(DEABCY)a(++=
+=
F٣J٩EאאאאF٣J٣KE E
ABC
DE
Y = ABC + DE
A
B
C
D FE E
ABC
Y = ABC + D + E
A
B
C
D FE
F)ED(C)BA(Y +++=
BA +
A
B C)BA( +
C
ED +D
EF)ED( +
F
F٣J٨EאאאF٣J٧EאאORJאK
א١٤٧ א א א
אאאאא א
- ٧٠ -
אאאאאW
אW
אאאW
א(A + B)(C + D)אORאANDא،
אאאאORאאאאAND٣J١١FKEאאא٣J١١FEאאANDJאK
F٣J١١EאאאF٣J١٠EאאANDJאK
F٣J١٢EאאNORאאא،אאANDJאKא(Y)אW
)DC()BA(Y +++=
)DC()BA(Y +•+=
)DC()BA(Y +•+=
≡ (A + B) (C + D)
BA +A
B
C
D
(A + B) (C + D)
BA +A
DC +
B
C
D FE FE
(A + B) (C + D)
D C
BA +A
DC +
B
F٣J١٠EאאאNORK
א١٤٧ א א א
אאאאא א
- ٧١ -
אאANDJאאאNORאאF٣J١٣KE
F٣J١٣EאאאאF٣J١٢KE
)FED)(CBA(]FED[]CBA[
]F)ED([]C)BA([Y
++=
+++=
+++++=
Y
F)ED( ++
C)BA( ++
C
A
B BA +
F
D
E ED +
F٣J١٢EאאNORK
FED +
CBA +
C
F
D E
BABA
ED
F)ED( )CBA(Y ++=
א١٤٧ א א א
אאאאא א
- ٧٢ -
F٣J٤WEאאאאאNORW
אWאאF٣J١٤KE
F٣J١٤EאאאאאNORK
٣J٥Karnaugh MapK-אא،אאא
אאKאאאאאאאאא
،אאאאאאאאאKK
אאאאK،א
)array (א)cells(،אאאKאאאא
אK،،،אאאא
،אאאKאאאאאאא
אאאאא
)Quine - McClusky (אאאאאאKאאא
)ED(CBAY ++=
E
CBACBA =++
D
C
A
B
)ED(CBAY ++=
א١٤٧ א א א
אאאאא א
- ٧٣ -
אא،Kאא823 =אא16 24 =K
٣J٦אאאSimplification using Karnaugh-map אאאFאKE
F٣J١٥E،א)B ، A(א)B,A(FאE(00,01,10,11)K
Y B A
0 0
1 0
0 1
A B 1 1
F٣J١٥EאK
אאאאKא)Input Labels(אF٣J١٦E
אאKאא،אA،אאאAאאKאאBאא
א،אBאאאK،אאאאBAKא
AB
BA
B B
A
A
BA
BA
BA
BA
BA
א١٤٧ א א א
אאאאא א
- ٧٤ -
F٣J١٦EF22 = 4KE
٣J١٧FE،٣J١٧FEאFE،אFKE
F٣J١٧EאאK
א،אאאKאא،٣אJ١٨FKE
B B
A
A
CBBCCBCB
A
A
DCCDDCDC
BA
BA
AB
BAFE
FE
א١٤٧ א א א
אאאאא א
- ٧٥ -
،אאאאאאא(1)אאאאאOR
٣J١٨FKEאאאא٣אJ١٨FKEאא
אאא٣J١٨FKE
א١٤٧ א א א
אאאאא א
- ٧٦ -
א א
Y B A
0 0 0
0 1 0
1 0 1
1 1 1
FFEEFE
F٣J١٨EאאאK
אאאאאאK(1)אא
(1)א،אא(0)א(0)אאK(1)אא
אFBAEאאא،FABKEאא)B A ,BA((0)،א(0)אאK
אאאאComplements)Eא،1AA =+Kאאא
٣J١٨FEא،אאאאK
A
A
Y
FE
BA
BA
1
0
B B
0
1
BABAY +=
1
0
B B
A
A
0
1A
Y
BAA B FE
BAA B
FE
א١٤٧ א א א
אאאאא א
- ٧٧ -
א٣J١٨FEאא
)adjacent cells(אKאאאא،Kאאא
)1(א٣J١٨FEאאאאKאאאBAAB,B،B،א
،אAW ABBAY += FאאאE
A1A)BB(AY
=•=+=
אאאאאאא٣J١٨FEא
א)Y(א)A(Kאאא٣J١٨FKE
F٣J٥WEאאא٣J١٩FEאK
אWאא،א،א٣J١٩FKE
אאא1(א(א٣J١٩FEאאא
٣J١٩FKE)0(אא،אאא٣J١٩FEאאאאאא،FאאE
אKאאאAA ,אCBאאא،CC,אBAK
אאאאאאאאא،א٣J١٩FKEאאאא
אANDאא OR אאא١٦אאאא،
א١٤٧ א א א
אאאאא א
- ٧٨ -
אANDאORאאא،אא٦א٣J١٩FKE
אא
Y C B A 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1
FE
F٣J١٩EאאK
1(א's(אFאEאא،،2KF٣J٢٠E،א
אאאאKאאאאF1'sEאאא
אKאאאא،אאאFאא
،א،אאאאאKE
FE CBBA
CBBCCBCB
A
A 11
1
1Y
FECBBAY +=
BA B C CA
א١٤٧ א א א
אאאאא א
- ٧٩ -
FE FE
D
B
BA
DCCDDCDC
AB
BA
1 1 1 1
1 1
0 1 1 0
1 1 1 1
BA
DBYDCBADCABDCBADCBA
ABCDCDBABCDADCBADCBACDBADCBADCBAY
+=
++++
++++
+++=
FאE FאE DBBADCY
DCBACDBADCBADCBADABCDCABDCABDBCADCBADCBADCBAY
++=
+++
++++
+++=
FאE
DB
BA
BA
DCCDDCDC
BA
0 1 0 0
1 1 0 1
1 1 0 1
1 1 1 1
BA
AB DC
F٣J٢٠EאאK
FאE
FאE
CAB
DA
BA
AD
DCCDDCDC
BA
1 1 1 1
1 0 0 1
1 1 1 0
0 1 1 0
FאECDBADCBAABCDDCABDCABDBCADCBADCBACDBADCBADCBAY
+++
++++
+++=
BADBAADCABY +++=
FE
BA
BA
CBD
DCBACDBADCBADABCDCABDBCABCDADCBADCBACDBADCBAY
+++
++++
+++=
FאEDCBCAY ++= FאE
FE
0
0
0
0 1
CA
1
1
1
1
1
1 1
1 1
DCCDDC
BA
BA
AB
BA
1
א١٤٧ א א א
אאאאא א
- ٨٠ -
٣J٦Wאאאאאא٣J٢١FEאK
אא
Y D C B A 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 1 1 1 1
٣J٢١FEאאאאK
אאאאאאא)Y(א(1)א،٣J٢١FKE
אאאאW
ABCDCDBABCDADCBACDBADCBAY +++++=
אאא٣J٢١FE،אאא)Y(אאאK
א١٤٧ א א א
אאאאא א
- ٨١ -
٣J٢١FEא٣J٦K
٣J٢١FEאא)1's(Kאאאא
אBאBאCא،CאDAKאאא
אאB،B،A،AאCDKאאאW CD DAY +=
٣J٧אאאאBinary Adders and Subtractors אאאאאאאאא
אאאאאאא،אKאאאאאאאאא
אאאאאאאאאK٣J٧J١אאאThe Half-Adder Circuit
א،אאאאF٣J٣EאאאאBA ,אא[Sum(S)]אאא])C( [Carry.
DA
CD
BA
DCCDDCDC
AB
BA
0 1 1 0
0 1 1 0
0 0 1 0
0 0 1 0
א١٤٧ א א א
אאאאא א
- ٨٢ -
אא C S B A
0 + 0 = 0 0 0 0 0 0 + 1 = 1 0 1 1 0 1 + 0 = 1 0 1 0 1 1 + 1 = 102 or 210 1 0 א 1 0 1 1
F٣J٣EאאאאK
אא )S(אאא)XOR(Kאאא)c(אאANDK٣J٢٢FE
אאאB,AאאS,CאאאאKאאאאK
FEFE
F٣J٢٢EאאאאK
אאאאא٣J٢٢FEאHAFdderAalf HEאאKאאאאS,C
א،אאW
ABC
BABAS=
+=
٣J٧J٢אאאThe Full-Adder Circuit אאאא)2-bits(
אאאא)carry(،אאא
CS
B A
HA≡C(carry)
S(sum)A א
א
B
א١٤٧ א א א
אאאאא א
- ٨٣ -
)bits(אאא،אאאאא
אאאאא،אKאאאאא)bits(،א
אא،A,BאאאאאCinFInput carryEאאאאאKא
)Carry ( ،א)Sum.(אאאאF٣J٤KE
א א C S Cin B A 0 + 0 + 0 = 0 0 0 0 0 0
0 + 0 + 1 = 1 0 1 1 0 0
0 + 1 + 0 = 1 0 1 0 1 0
0 + 1 + 1 = 102 or 210 1 0א 1 0 1 1 0
1 + 0 + 0 = 1 0 1 0 0 1
1 + 0 + 1 = 102 or 210 1 0 א 1 0 1 0 1
1 + 1 + 0 = 102 or 210 1 0 א 1 0 0 1 1
1 + 1 + 1 = 112 or 310 1 1 א 1 1 1 1 1
F٣J٤EאאאאK
אאאאאאC,B,AאאF823 =EאKאאS,Cא
אאאאאKאאאאCS,אW
inininin
inininin
ABCCABCBABCAC
ABCCBACBACBAS
+++=
+++=
א١٤٧ א א א
אאאאא א
- ٨٤ -
אא،אאאאאאאאאאSW
inin
inininin
C)ABBA(C)BABA(
ABCCBACBACBAS
+++=
+++=
אאBABA +XORאא،ABBA + XNOR
אאאאW
inin C)BA(C)BA(S ⊕+⊕=
אXOR)BA( ⊕אinCאאSW
inin CBAC)BA(S ⊕⊕=⊕⊕=
SאאXORא،B,Aא
אinCKאCאאW
)1CC(ABC)BA()CC(ABC)BABA(
ABCCABCBABCAC
ininin
ininin
inininin
=+⇐+⊕=
+++=
+++=
SCא٣J٢٣FKEאאאא٣אJ٢٣FEאFAא
)dderAull F (אאK
א١٤٧ א א א
אאאאא א
- ٨٥ -
F٣J٢٣EאאאאK
אא٣J٢٣FEאאאאאORאאאא2אOR
אF٣J٢٤KE
٣J٧J٣אאאHalf Subtractor Circuit
אאאKאאאאK
א،אאאאאאK،א)bit(אאאא
)bit(אא)difference(K،אאא
Cin C(carry)
S(sum)
A
B
C S
B A
FA≡
Cin
FE FE
C
S
C
S B
A
B
A
Cin
C
S
HA
HA
F٣J٢٤EאאאK
א١٤٧ א א א
אאאאא א
- ٨٦ -
א)1()Borrowed(אאK،K
אאאא)2-bits(א)1(אאKA א
BK)A – B(אB, A KBA ≥،א)Difference bit.(אאW0 – 0 = 0, 1 – 0 = 1, 1 – 1 = 0א
A<B0 – 1א،אא)1(אאKאאא2،אא،אא)10(
אKא)2(،1 = 1 – 2אKא،אא)D (אא
)B0(Kאאאאאאאא
F٣J٥KEאא)D(א،)0B(אאאW
BAB
BABAD
0 =
+=
אאB0 D B A 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 1
F٣J٥EאאאאK
א)D(א(S)אאXORא،)0B(א)C(אאאA
א)0B(אANDאA،BK٣J٢٥FE،אא٣J٢٥FEא
א،אHSא)ubtractorSalf H(K
א١٤٧ א א א
אאאאא א
- ٨٧ -
٣J٧J٤אאאThe Full-Subtractor Circuit אאאא2(א-bits (אא
)1(אאKאאKאאinB,B,Aא)A(א)B(אא) niB(אKא0B,DאאאKאאאאF٣J٦KE
א א B0 D Bin B A 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 1 1 1
F٣J٦EאאאאK
אאאאא0's,1'sאאאK0's,1'sאאאinBBA −−Kא0אBin =אאאאK
1B0,B0,A in ===)1(אאא1B0 =)2(A،2 – 0 – 1 = 1،1D =K
B0
B0(borrow)
D(difference)A
א
D
B A
B
HS≡א
F٣J٢٥EאאאאK
א١٤٧ א א א
אאאאא א
- ٨٨ -
1B,1B0,A in ===)1(אאא1B0 =،A = 2،2 – 1 – 1 = 0،0D =K
1B0,B,1A in ===،A – B – Bin = 0א0B0 =،0D =Kא1B,1B,1A in ===)1(אאא1B0 =،A=3،3 – 1 – 1 = 1،1D =K
אאאאאW
(S)،אאאאאW
א(B0)אא،W
א(B0), (D)٣J٢٦FEא،אאא٣אJ٢٦FEא،FSא)ubtractorSull F(
אאKאאא٣J٢٦FEאאא
אאORאא،א2אא
ORאF٣J٢٧KE
inininin ABBBBABBABBAD +++=
inBBAinBB)(AD ⊕⊕=⊕⊕=
)1BB(BA)BA(BB
)BB(BA)ABBA(BABBBBABBABBAB
ininin0
ininin
inininin0
=+⇐+⊕=
+++=
+++=
א١٤٧ א א א
אאאאא א
- ٨٩ -
Bin B0
DA B
D
B A
FS ≡
Bin
FE FE B0
F٣J٢٦EאאאאK
B0
D
B0
D B
A
B
A
Bin
B0
D
HS
HS
F٣J٢٧EאאאK
א١٤٧ א א א
אאאאא א
- ٩٠ -
١EאאאW a) b)
c) d)
٢EאאאאאNANDW a) b) c) d)
٣EאאאאאNORW a) b)
c) d)
٤EאאאאאW
א א Y C B A
1 0 0 0
1 1 0 0
0 0 1 0
0 1 1 0
1 0 0 1
0 1 0 1
1 0 1 1
1 1 1 1
)DC(BA + )EFCD(AB +
DABC)DCBA( ++++ )DCBA()DCBA( +++
EDABCD + DABCBA ++EDCBA ++ CABABCBCACBA +++
)BA()CBA( +++ )ED(CBA ++
)FED()CBA( ++ )DC()BA( +++
א١٤٧ א א א
אאאאא א
- ٩١ -
٥EאאאאאאW
a)
b)
c)
d)
٦EאאאאF٣J٢٣Eאא،(1 or 0)אאW
a) A = 1, B = 1, Cin = 1 b) A = 0, B = 1, Cin = 1 c) A = 0, B = 1, Cin = 0 d) A = 1, B = 1, Cin = 0
٧EאאאאאאאאאאW a) S = 0, Cout = 0 b) S = 1, Cout = 0 c) S = 1, Cout = 1 d) S = 0, Cout = 1
٨EאאאאF٣J٢٦Eאא،(1 or 0)אאW
a) A = 1, B = 1, Bin = 1 b) A = 1, B = 0, Bin = 1 c) A = 1, B = 1, Bin = 0 d) A = 0, B = 1, Bin = 1
DBCADCABDCBADABCDCBADCBAF1 +++++=
DCBADABCDBCADCABDCBADCBADABCF2 ++++++=
DCBADCABDCABDCBADCBAF3 ++++=
CDBADCBADBCABCDADCBADCBADCBADCBAF4 ++++++++=
אאאאאאאא
אא
אאאã¹]<gè…‚jÖ]æ<ËÖ]<Üé×Ãj×Ö<íÚ^ÃÖ]<퉉ö¹]
אאאא
א
אא
א
٤
אאא ١٤٧ א א
אאאא א
- ٩٢ -
אאא
אאW• אאאאאאK • אאאאאאK • אאאאJאאאK • אאאאK • אא555אK • אאאאאK • אאאאאאאאאאאK • אאאאאאאאאK
אאא ١٤٧ א א
אאאא א
- ٩٣ -
אא٤J١Introduction
אאאאאא،אאא)Combinational Logic Circuits(אאאא
א،אאאאאאאאאא،אאאאא) Sequential Logic Circuits (אאאא
א)Memory(אאאאאאאK
אא،אאאאאאאאאאאאאאא)Flip-Flop Circuit(، אא
אאא)0(א)1(Kאאאא)1(א)1(א،
אא)0(א)0(Kאאאאאאאאאאאאא
אא)Bistable Multivibrator.(אאאאאNANDאNORאא)Digital Integrated Circuits(K
אאאאא)Timers(،אאא)Counters(،אא)Shift Registers(אאא
אK٤J٢אLatches
אאאאאאאאKאאאאאא
אאאאאאאאאKאאאאאא
Kאא
אאא ١٤٧ א א
אאאא א
- ٩٤ -
א)Latch(אאאאא)Bistable Multivibrator(KF٤J١EאאאאאS-R
S אאא"1")Set Input(Rאאא"0")Reset Input(
QאQאK
F٤J١EאאאאאS-RK
אא)Set Condition(0=Q Q =1, )Reset Condition(1= Q0, .Q =א
אאSא)1(אאQ = 1FאאEאQאאא،א
0= QKאאRא Q = 0FאאEא1א= Qא،S,Rאא)1(
אא)unpredictable(،אאאK
אאS-RאNORאאאאאאאאאF٤J٢KE
F٤J٢EאאS-RאאאK
R
Q
Q
S
output Q
Q output
RESETINPUT
SET INPUT
R
S Q
Q
אאא ١٤٧ א א
אאאא א
- ٩٥ -
אאאאאNOR)1(FאאאEא،אאאאאא
F٤J١Eאאאאא،אאאא)Active High Inputs(K
א א א
(Mode of Operation) Q R S אFאE
No Change Q0 0 0
אא Latch RESETS
0 1 0
אא Latch SETS
1 0 1
א Invalid condition
? 1 1
F٤J١EאאאS-RאאאK
אאאW١- אא)0(אS,Rאא
א)Q(FאאאEאאאאK
٢- אאאR)0()1(אאQ)0(Q = 0 FאאEאא،אאא
Q = 0 K ٣- אאאS )0()1(אאא
Q)0()1(Q = 1FאאEא،אאאאQ = 1K
٤- א1(א(אS,RאאאאאNORאאאא،
אK
אאא ١٤٧ א א
אאאא א
- ٩٦ -
٥- אאאאא،אאאאא،אא
KאאאאNANDF٤J٣Eאאא
אNAND)0(אאאאאF٤J٢Eאאאאאאאאא)Active Low Inputs(K
F٤J٣EאאS-RאאאK
א א א (Mode of Operation) Q R S
א Invalid condition
? 0 0
אא Latch SETS
1 1 0
אא Latch RESETS
0 0 1
אFאE No Change
Q0 1 1
F٤J٢EאאאS-RאאאK
אאאW١- אא)1(אאאאאQ
FאאKE ٢- אאא0= Sא،1= Rאא
)1(אא،אאאQ = 1K
R
Q
Q
S
אאא ١٤٧ א א
אאאא א
- ٩٧ -
٣- אאא1 = Sא،0= Rאא)0(אא،אאאא،Q = 0
K ٤- א)0(אאאאאא
NANDאK אF٤J٤Eאא)Logic Symbol(אאאאא
אאאאאאK
FFEE
F٤J٤EאאאאאאאאאKאאאאאאאא
R,Sא)Q(K0R0,S ==،אאK
٤J١WאאR,SF٤J٥KEאא)Q(אאאQאQ = 0K
אW
F٤J٥EאאאאK
Q
S
R
Q
Q
R
S
Q
Q S
R Q
QS
QR
Q
אאא ١٤٧ א א
אאאא א
- ٩٨ -
٤J٣אS-RאאClocked S-R Flip–Flop אS-RRS−אאאאאא
אא)Q(אאאא،אאאאאאאאאאאאאK
אאאאאFאEאאאאאא
א،אאאS-RאאאאK
אאא،CK((אא))Clock Pulseאאא
אאאאאKF٤J٦EאאS-Rאא
אאא)CK(K
FFEE
F٤J٦EאאS-RאאKא٤J٦FEאאא
אS-Rאא)Positive Edge Trigger(א0(א()1(א،٤J٦FEאאאאא
אאא)Negative Edge Trigger (אא)1()0(K
F٤J٧EאאS-RאאאאNANDא،NANDאאאאKאא
Q
Q
Q
Q S
R
CK
S
R
CK
אאא ١٤٧ א א
אאאא א
- ٩٩ -
אS,Rא)Q(אאאאאאאK
F٤J٧EאאS-RאאK
אF٤J٣EאS-RאאאאW١J אאCKאא،אS,Rאא)0(
אאאאאK٢J אאRא)S = 0,R = 1(אא)0(
)1(א)0(אאא)Reset.( ٣J אאSאא)S = 1,R = 0(אא)0(
)1(אQ = 1אאא)Set.( אאS = 1, R = 1א
אKא א א
(Mode of Operation) Q CK R S אFאE
No Change Q0 X 0 0
אא Latch RESETS
0
1 0
אא Latch SETS
1
0 1
א Invalid condition
?
1 1
א(0)א(1)Z↑ZX
אאאZQ0
F٤J٣EאאאS-RאאK
CK
R
Q
Q
S
אאא ١٤٧ א א
אאאא א
- ١٠٠ -
אאS-Rאאא]א)1()0([אאאאאא
אא)1()0(K٤J٢Wאא)Q (אאS-RאF٤J٦Eא،
אS,R,CKF٤J٧KEאאאQ = 0 אאK
F٤J٧EאאאאS-RאאK
אW١- אאאS = 0, R = 0א،)Q(Q = 0K٢- אאאS = 0, R = 1א،Q = 0)Reset(K ٣- אאאS = 1, R = 0א،Q )1(Q = 1)Set(K ٤- אאאאS = 0, R = 1א،Q = 0)Reset.( ٥- אאאS = 1, R = 0א،=1 Q)Set(K ٦- אאאS = 1, R = 0 א،)1(Q = 1 K
654 3 2 1CK
S
R
Q
אאא ١٤٧ א א
אאאא א
- ١٠١ -
٤J٤אאאD D-Type Flip-FlopאאאאDאאא)Single Bit(
0(א1(KאאאS-RאאאאDF٤J٨KE
F٤J٨EאאאDK
אאאDאאDאא
CKKאDאא)1(אאאCK،אאא1(א([Set]א،אS = 1א،R = 0
אאאS-RאאF٤J٣EאQ = 1KאDאא)0(אאאCK،אא
אא)0([Reset]،אאS = 0א،R = 1 F٤J٣EאQ = 0Kאא)Set()1(א
א،אא)0()0(אאKאאאאאDאאאא
אא )Positive Edge Trigger(אF٤J٤KE
א א א (Mode of Operation) Q CK D
אא(SET) (stores a 1)
1
1
אא(RESET) (stores a 0)
0
0
א(0)א(1)Z↑
F٤J٣EאאאD אאK
D
Q
Q
CK
R
S
אאא ١٤٧ א א
אאאא א
- ١٠٢ -
אא)Q(א)D(אאKאF٤J٩EאאDאאא)D(
אא )CK(אאאKאF٤J١٠EאאDאNANDK
F٤J١٠EאאDאNANDKF٤J٩EאאDK
٤J٣WאאFQEאאאDאF٤J٩EאאFDEF٤J١١KEאאאQ = 0 אK
אW
F٤J١١EאאאאאDK
א)Q(א)D(אאאא)0()1(אאK
Q
Q
D
CK
R
Q
Q
S
CK
D
CKD
Q
אאא ١٤٧ א א
אאאא א
- ١٠٣ -
٤J٥אJ-KאאJ-K Flip FlopאאJ-KאאאאKאאJ,Kאא
،אאאאS-RאאKאJ-KאS-Rאאא
אאאא)Set(אא)Reset.(אאJ-KאאS-RK
אF٤J١٢EאאJ-KאאאאKאאאS-Rאאא
אאאJ,Kאא)1(אאK
F٤J١٢EאאJ-KאאאאK
F٤J١٢EאאאאאSRאQ،QאK
אF٤J٥EאJ-KאאאאJ,K)0(אאאא،
א)Reset(א)0(אאJ = 0, K = 1א،אאאאאא)Set(J-KאאJ = 1, K = 0
אאKאאאאJ-Kא)Toggle(،אJ,Kאא)1(אQאא
אאאCKK
K
J
CK
Q
Q Q
Q
CK
J
K
אאא ١٤٧ א א
אאאא א
- ١٠٤ -
א א א
(Mode of Operation) Q CK K J אFאE
No Change Q0
0 0
אא (RESET)
0
1 0
אא (SET)
1
0 1
א Toggle 0Q
1 1
א(1)א(0)Z↓אאאZQ0
F٤J٥EאJ-KאאK
٤J٤Wאא)Q(אאJ-KאF٤J١٢EאאJ-KCKF٤J١٣KEאא
Q = 0אKאW
F٤J١٣EאאאאJ-KאאK
١- ،אאאJ,K)1(אאאQ א)1(K
٢- אאאאאאאJ = K = 0K ٣- ،אאJ = 0, K = 1)Reset(Q = 0K
54321CK
J
K
Q
אאא ١٤٧ א א
אאאא א
- ١٠٥ -
٤- ،אאאJ = 1, K = 0)Set(Q = 1K ٥- א)Set(אאאJ,KאQ
1(א(K
٤J٦אאאT T-Type Flip-Flop אאאTאאJ-Kאא
אJ,KאF٤J١٤Eאא،TאאTאאKאTא)Toggle(
אאKא)T(א)1(אCKאא،אא
אאאCKאאאאאאאאאאאCKF٤J١٤KE
F٤J١٤EאאאאאTK
אאאאTF٤J٦KE
א א א (Mode of Operation) Q CK T
אFאE No Change
Q0
0
א Toggle 0Q
1
א(1)א(0)Z↓אאאZQ0
F٤J٥EאאTK
T
Q
Q J
CK
K
אאא ١٤٧ א א
אאאא א
- ١٠٦ -
٤J٥WאאQאאא)T(אF٤J١٤EאאTאCKF٤J١٥Eאא
Q = 0 אKאW
F٤J١٥EאאאאאTKאאQאT = 1،אאא
אאאT = 0QQ = 0אא،T = 1אQ)0()1(אK
٤J٧א–אMaster-Slave Flip-Flop
אאאאאאאאאאא)Edge Triggered(K
אאאאא)Pulse Triggered(אא–א)Master-Slave(،אא
אאא)Complete Clock Pulse(אאאK٤J١٦FEאS-RאאJא،א
S-Rאאא)Master(א)Slave(אא،)Master(אאאא)CK(אא،)Slave(
אא)CK(K
CK
T
Q
אאא ١٤٧ א א
אאאא א
- ١٠٧ -
٤J١٦FEאאS-RאJאK
אאCK،CK٤J١٦FE،אא)Master(אאאא)CK(אא،
)Slave(אאאאאאאא)CK(K
Q،QאS,RWאאWאא)High()CK(אא)Master(
א)Enabled(אאא)Set (אא)Reset(אאS,RK
אאWאא)Low()CK(אא) slave (א)Enabled(אQאאאאYK
אא٤J١٦FEאאאS-RאJאKאאאאS-RאאK
א)CK(אאאאא)High(א)Low(אאK
٤J١٦FEאאאS-RאJ،אאא)CK(אt0t5אאא
S,RK
Slave Master
CK
Y
Y
R
CK
S
Q
Q
אאא ١٤٧ א א
אאאא א
- ١٠٨ -
• אt0אא،)Master (א)Enabled(אא)High(אא)CK(א S = 1, R = 0אא
)Set(א،אאY = 1)0Y =(K • אt1אא،)Disabled(אא)Low(
CKאא،)Slave(א)Enabled(אא)High(CKKY,Y،אאאאQ
אא)Set (Q = 1KאאאאאאאF
0Y,1Y ==0אQ,1Q ==אא1CK =KEאאאאאאאK
א א א (Mode of Operation) Q CK R S
אFאE Q0 0 0 אא (RESET) 0 1 0
אא(SET) 1 0 1 א 1 1 ؟
٤J١٦FEאאאS-RאJאK
אאא ١٤٧ א א
אאאא א
- ١٠٩ -
٤J١٦FEאאאאS-RאאK
• אt2אא،אאא،)High(
CKאS = 0, R = 1א1Y,0Y ==אא)Reset.(
• אt3אאאא،)Low(CK ،אאאKאאאא)Reset(
אQ = 0K• אt4א،S,Rא)Low(אY
אא،א)Y = 0(Kאאt4،אSא)High(אאY = 1K
MasterEnable
t5 t3 t4 t1 t2 t0
MasterEnable
Q
)setReSlave(YY (Slave Set)
CK
Slave Enable
Slave Enable
Slave Enabl
MasterEnable
MasterEnable
YY
R (RESET)
S (SET)
CK
كال أشنبضات التابع
(Master)
أشكات نبضاتالمتبوع (Slave)
אאא ١٤٧ א א
אאאא א
- ١١٠ -
• אt5،אאאאא،אY = 1אQQ = 1K
א א א (Mode of Operation) Q CK D
אא(SET)(stores a 1)
1
1
אא(RESET)(stores a 0)
0
0
F٤J١٧EאאאDאJאאאK
٤J١٧FEאאDא–،٤אJ١٧FEאאKאאS-Rא–،אאאDא–א
QKאCKאא٤J١٨FEאאJ-Kא–א،٤אJ١٨FE
אאאאKא٤J١٨FEאאאJ-Kא–אאא)Q(
Kא–אS-Rאאאאא
FE
Clock in
D
CK
Q
Q
FE
SCK
R
S
CK
R
אאא ١٤٧ א א
אאאא א
- ١١١ -
٤J١٨FEאאJ-KאJאK
א א א (Mode of Operation) Q CK K J
אFאE Q0 0 0 אא (RESET) 0 1 0
אא(SET) 1 0 1 א(Toggle) 0Q 1 1
٤J١٨FEאאאJ-KאJאK
Slave Master
CK
Y
Y
K
CK
J
Q
Q
אאא ١٤٧ א א
אאאא א
- ١١٢ -
٤J١٨FEאאאJ-KאJאK
אאאאאאKאאא)PRESET()PRE(א
אא)CLEAR()CLR(אF٤J١٩Eאאא S-R PRE،CLRKאא
،אאאאאא)SET(Q = 1،אא)RESET(Q = 0 א،
אQאKאאא)RESET(א)CLEAR(אאאאKא)PRE(
א،אQא)1(0PRE =،
Q
Y
Y
CK
Y
Y
J
ME ME ME ME ME ME ME ME ME ME
SE SE SE SE SE SE SE SE SE
CK
K
ME = Master Enabled
(Master)أشكال نبضات التابع
SE = Slave Enabled
(Slave)أشكال نبضات المتبوع
אאא ١٤٧ א א
אאאא א
- ١١٣ -
א)CLR(אQא)0(0CLR =KF٤J٧EאאאאS-R
1אCLR =א0PRE =FEאQ)1(אא،R S, CK,Kאאא1PRE =
0CLR =FEאאQ)0(אאR S, CK,K
F٤J١٩EאאאאS-RPRE،CLRK
א א א (Mode of Operation) Q R S CK
אא(SET) 1 X X X 1 0 אא (RESET) 0 X X X 0 1
א ? X X X 0 0
F٤J٧EאPRE،CLRאאS-RK
PRE CLR
CLR
PRE
Q
Q
R
CK
S
אאא ١٤٧ א א
אאאא א
- ١١٤ -
אא
٤J٨אא Timer Circuits א،אאא،אאא
א)Clock Signal(אאאאKאKאא)Sharp(אא)Positive Edge(
אאא)Negative Edge(אאאאKאS-R,D-Type J-K,אאאאאא
)Bistable Multivibrator(،)bi()Set and Reset States.(א)Astable Multivibrator(אאא،א
אאא،אאאא)Monostable Multivibrator(אאאא)Mono()Triggered()Rectangular Pulse()Fixed Duration(K٤J٨J١אאאאאAstable Multivibrator Circuit
אאאאאאאא)Free running(אאF٤J٢٠Eאא)Inverter()Schmitt-trigger (K
F٤J٢٠EאאאאאK
∫ ∫ 1(0)0 (1)
C
R
Discharge FאE
Charge FאE+5V
+
אאא ١٤٧ א א
אאאא א
- ١١٥ -
،אאאאא)0(אא،)Low(אא)Not()High .(
א)C(אא)R(אאא،אאCR,אאאא،)High(
אKאאא(Low)،אKאאא)Low(،אא(High)אK
٤J٨J٢אאאאאאMonostable Multivibrator Circuit ٤J٢١FEאאאאאאKא
)Trigger(א)Low(אא،Q)Low(،אאאNOR(High)אאא(Low)אאא
אKא(High)א،א NOR א)Low(Kא
،אאאNOR،אא(High))Low( אא(High)אQאא
٤J٢١FKEאאQאאאNORאאא)Low( אאK
F٤J٢١EאאאאאאאK
Output Pulse (Q)
Input Trigger (T)
C
R
+5V
+
FE
Output Pulse (Q)
Input Trigger (T)
FE
אאא ١٤٧ א א
אאאא א
- ١١٦ -
אאNORאא)resistor–capacitor network(،אאK
אאCאR،אאאא(High)א)Low(אQK
٤J٨J٣אא555The 555 Timer Circuit אא555،אאאא
)IC(אאF٤J٢٢Eא،555א،אאאאאΩK5K
F٤J٢٢Eאא555K
א،א
)Astable mode(אאאאא)Monostable mode(אא)Frequency Divider()Modulator(אאא
אK
٤J٨J٣J١א555אאאא 555 Timer as an Astable Multivibrator
Ground FאE
Trigger FאE
OutputFאE
Reset FאאE
Control VoltageFאE
Threshold FאE
DischargeFאE
+VCC
FאE5678
1 2 3 4
אאא ١٤٧ א א
אאאא א
- ١١٧ -
٤J٢٣FEא555אא)Astable(א)Free running(Kאא٤J٢٣FEאאC،א
אא+VccFאE)0(K
٤J٢٣FEא555אאK
Output FאE
RL
+5V
+
555 Timer
Inverter FE
Inverting Buffer/Driver
QS-R Flip-Flop
R
S
Discharge TransistorFאאE
5KΩ
1/3 VCC
5KΩ
2/3 VCC
5KΩ
Comparator(B)
Comparator(A)
RA
RB
C
1
23
4
5
6
7
8
-
+
-
+
אאא ١٤٧ א א
אאאא א
- ١١٨ -
٤J٢٣FEאCאK
אאאאאS-Rא)High(]אT1א[Kאאאאא(Low)א
אאא)Discharge Transistor(אOFFKאאאאOFF،אא)C(אא
+VccאRA RB,KאT2،אאא
CCV32،אאA(High) אאCCV
31
אאא(RESET)Q = 0Kאא)3(555א(Low)،אא(High)א،ONK
אאאאON،אCKא
T3אא،CCV31،אB
א(High)אאS-Rא(SET)Q = 1א،אKאאאOFF،C
אKא٤J٢٣FEא،CאRA RB,א
CCV32א،RBאCCV
31Kאtp) Positive time (
אW
tp tn
T1 T2 T3 T4 T5
2/3 VCC
Voltage Across "C"
1/3 VCC
(+VCC)
(0)Output
אאא ١٤٧ א א
אאאא א
- ١١٩ -
C)RR(7.0t BAp += אtn) Negative time(אW
CR7.0t Bn =
،tnWאtpאEאאTFא
T = tp + tn C)R2R(7.0 BA +=
א555אאW
C)R2R(7.01
T1f
BA +==
אאאW
C)R2R(43.1f
BA +=
٤J٨J٣Jא٢אאאאא
555 Timer as a Monostable Multivibrator ٤J٢٤FEא555אאאאא
)one-shot.(אא٤J٢٤FEאא)Input - trigger(אא،א،555Kא
)Pw(אאCRA,KאT1٤J٢٤FEאא،S-R)RESET(
)Low(Q = 0Kאא(Low)אאS-Rא،א)inverted and buffered(א،אא
555א)3(0V(Low)Kא(Low)אאS-R(High)א
،KאאאאONא،א
אאא ١٤٧ א א
אאאא א
- ١٢٠ -
אT2א،)Trigger(א(2)אא555
אאKאאאא BCCV31،
אB(High)אא،S-Rא)SET(אQ = 1Kאא (High)אאS-Rאאא)3(555א
(High)אאאOFFK
٤J٢٤FE555אאאאK
Output
RL
+5V
555 Timer
Inverter
Inverting Buffer/Driver
QS-R Flip-Flop
R
S
Discharge Transistor
5KΩ
1/3 VCC
5KΩ
2/3 VCC
5KΩ
Comparator(B)
Comparator(A)
RA
C
1
23
4
5
6
7
8
-
+
-
+
+
TriggerInput
אאא ١٤٧ א א
אאאא א
- ١٢١ -
٤J٢٤FEאאCאאK
אאCאאRA+VCCא٤J٢٤FKEא555א(High)א
אCCV32Kא)T3(،אA(High)،
אאS-Rא)RESET(אא،)3(א(Low)אאא،ONאC
Kאאאאאאאא
Kאא)Leading edge(،אאא
א)Trailing edge(אאCאRAאאKאאאW
CR1.1P Aw =
T1 T2
2/3 VCC
Voltage Across "C"
1/3 VCC
Output
0 V
Trigger Input
אאא ١٤٧ א א
אאאא א
- ١٢٢ -
٤J٩אאShift Registers،אא،אאאאאא
אאאא)bit(אאאאא،א،
אאאאא)Buffer Register(אאא)Shift Left (א)Shift
Right(אאא)Serial Data(א)Parallel Data(אאא)Shift Registers(K
٤J٩J١אBuffer Registersא)Digital word(
אא)bits(K٤J٢٥FEא)4-stages(אאאאD אאאאא)Positive edge-triggered(K
٤J٢٥FEאאאאאאDK
CLR
CK
D1 D2 D3 D4
Q1 Q2 Q3 Q4
אאאא (4-bit word to be stored)
אאא(parallel data outputs)
FE
Q
QD
CLR
D Q
QCLR
Q
QCLR
D Q
QCLR
D
אאא ١٤٧ א א
אאאא א
- ١٢٣ -
٤J٢٥FEאא٤אJ٢٥FKE
אא4(א-bits(אאD4D3,D2,D1,אQ4Q3, Q2,Q1,א
אא)CK(Kאאא٤J٢٥FEאאאא
אQ4Q3, Q2,Q1,אאאאאKאאK
א،אאא،אאאאאJאא
)Parallel-in, Parallel-out Registers(Kא)Clear-input(אאא)active-low(אאFאKE
Clock
D1
D2
D3
D4
Q1
Q2
Q3
Q4
א Input data
א Output data
1
0
1
0
FE
אאא ١٤٧ א א
אאאא א
- ١٢٤ -
٤J٩J٢אאShift Registersאאאא)move(א)Shift(א
KאאאאאאF٤J٢٦KEW١- אאא–אא)(Serial-in, Serial-out Shift Registers
אא(SISO)K
٢- אאא–אא)Serial-in, Parallel-out Shift Registers(אא(SIPO).
٣Jאאא–אא) Parallel-in, Serial-out Shift Registers(אא(PISO)K
٤J٢٦FEאאK
Serial-in, serial-out (SISO) Shift Registers
Shift Right Shift Left
Rotate Right Rotate Left
Serial-In Serial-Out Serial-In
FE
Serial-in, parallel-out (SIPO) Shift Registers Parallel-in, Serial-out Shift (PISO) Registers
Parallel Data In
Parallel Data Out
Serial-In
Serial-Out
FE
אאא ١٤٧ א א
אאאא א
- ١٢٥ -
אאאאאW
٤J٩J٢J١אאאא–אאSerial-in, Serial-out (SISO) Shift registers
F٤J٨Eאאא،Kאאא0110אFאאEאאאא1001
אאאאK
אאאאאא
Q3 Q2 Q1 Q0Input Clock
0 1 1 0 ——1 1 0 1 1 1st
1 0 1 0 0 2nd
0 1 0 0 0 3rd
1 0 0 1 1 4th
F٤J٨EאאK
אא1(אst Clock pulse (אאאאאאאאאאאאאאאאאאKאאא)2nd Clock pulse(،
אא)0110(אאאאא1001(א(Kאאא،אאאK
،אאאאאאא(0110)אאאא،1001(א(אאאא
K
אאא ١٤٧ א א
אאאא א
- ١٢٦ -
אא،אאאאאKאאאאא
F٤J٢٧EאאאאאK
٤J٢٧FEאא)4-bits(אאאאDKאאאאDאאא)FF0(א،
אא)Q0(אDאאא)FF1(אאא،)Q1(
Serial Data Out
FF0 FF1 FF2 FF3SerialDataInput
ClockInput
FESISO Shift Right
D 2QD 1QD
CK
0QD
FF0FF1FF2FF3
SerialDataInput
ClockInput
Serial Data Out
FESISO Shift Left
SISO Rotate Right SISO Rotate Left
FE
D 0Q
CK
1QD
CK
2QD
CK
3Q
אאא ١٤٧ א א
אאאא א
- ١٢٧ -
אאאא)FF2(אאא،)Q2(אאאאא)FF3(،אאאאאאאאאאא
אKאא)Clock input(،אא
)Positive edge (אאא)1-bit(אא،אאאא–אאאאא
،אאאאאאאK
،אאא٤J٢٧FEאאDאאאאא–אא
)SISO Shift-Right Shift Register .(אאא٤J٢٧FEאאאאDאא–א
א)SISO Shift- Left Shift Register(Kאאא،א٤J٢٧FE،٤J٢٧FE
אאאא،אאאא–אאא
)SISO Rotate-Right(אא–אאא) SISO Rotate-Left (٤J٢٧FKE
٤J٩J٢J٢אאא–אאSerial-in, parallel out (SIPO) Shift registers
אF٤J٢٨Eאאאאאאאאא–אאK
אאאא،אאא)4-bits(אאא)Serial data input(אאאאאFא
אאKE
אאא ١٤٧ א א
אאאא א
- ١٢٨ -
F٤J٢٨EאאאאJאאK
)4-bits(אאאאאאKאאאאאאא
Q3,Q2,Q1,Q0)()4-bits(אאK٤J٩J٢J٣אאא–אא
Parallel-in, Serial-out (PISO) Shift registers F٤J٢٩Eאאאא
–אאאאאאDKאאאאLOAD/SHIFTKאLOAD/SHIFTא)Low(،
אאAND אא)Enabled(אאInverterאKאאאא
א)D3,D2,D1,D0(אאאאKאא)Clock pulse(،אאאא)Q3,Q2,Q1,Q0 .(
0Q 1Q3Q
FF0 FF1 FF2 FF3
CK CK
SerialDataInput
ClockInput
0Q
1Q 2Q 3Q
Parallel data outputs
D 2QD
CK
D D
CK
אאא ١٤٧ א א
אאאא א
- ١٢٩ -
F٤J٢٩EאאאJאאK
אLOAD/SHIFTא)High(،אאANDאא)Enabled(KאאאאQ0
אDאאא)FF1(א،Q1אאאא)FF2(،אQ2אאאא)FF3(K،אאאא
אאאאאאא)1-bit(אאאאFclock input.(
٤J٩J٢J٤אאאFאEShift Register Sequencer (Ring Counter) ٤J٣٠FEאאא
אאא)FF3(אאאFF0FאQ3D0KEאאאאאאאאאא
KאSRARTאLowאQ0אHigh)0PRE =(א، Q1,Q2,Q3אLowF0CLR =E
א٤J٣٠FKE
Parallel data inputs
ClockInput
0Q
1Q
2Q
3Q
FF0 FF1 FF2 FF3
CK CK CK
0D
1D
2D
3D
)loadfor0,shiftfor1(
control)LOAD/SHIFT(
Serial Out
D D D D
CK
אאא ١٤٧ א א
אאאא א
- ١٣٠ -
CK
0Q 1Q
2Q 3Q
FF0 FF1 FF2 FF3
CK CK CK
Clock
FE
0D
1D 2D 3
DPREPRE PRE PRE
CLRCLRCLRCLR
START
0Q 1Q
2Q 3Q
٤J٣٠FEאאאK
0 1 2 3 0 1 2 3 0 1 2
Clock
START
0Q
1Q
2Q
3Q
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
FE
٤J٣٠FEאאאK
אאא ١٤٧ א א
אאאא א
- ١٣١ -
אא Clock Pulses Q0 Q1 Q2 Q3
0 1 0 0 0 1 0 1 0 0 Four flip-flops will have 2 0 0 1 0 Four output states. 3 0 0 0 1
F٤J٩EאאאK
אאא(1000)א،אאא)1(אאאאאאאא
F٤J٩KE٤J٩J٢J٥אJohnson Counter
٤J٣١FEאא،אאאאאאאאא
F3QEאאאא)D0(K،אאאאאאאאא٤J٣١FEאאF٤J١٠E،1000،Q3
א(Low)،אא3Qא(High)אאאD0،אאאא)High inputs (א
אאאאאא)High(KQ3א(High)FאאאE،3Qא(Low)،
D0(Low)Kאאאאאא)Low inputs(אאאא)Low(K
Q3א)Low(FאאאE،3Qא(High)D0(High)אאאאK
Repeat Sequence
אאא ١٤٧ א א
אאאא א
- ١٣٢ -
F٤J٣١EאאאאאK
0Q 1Q
2Q 3Q
FF0 FF1 FF2 FF3
CK CK CK
Clock
FE
0D
1D 2D 3
DPREPRE PRE PRE
CLRCLRCLRCLR
0Q 1Q
2Q 3Q
0 1 2 3 4 5 6 7 0 1 2
Clock
START
0Q
1Q
2Q
3Q
FE
3Q
3Q
3
CK
אאא ١٤٧ א א
אאאא א
- ١٣٣ -
אא Clock
Pulses Q0 Q1 Q2 Q3
0 1 0 0 0 1
1 1 1 0 0 1
2 1 1 1 0 1 3 1 1 1 1 0 Four flip-flops will have
4 0 1 1 1 0 eight output states.
5 0 0 1 1 0
6 0 0 0 1 0
7 0 0 0 0 1
F٤J١٠EאאK
א،אאאאאאאאאאאאאFF٤J٩KEEאאאאאא
אאא،א٤J٣١FE)2 × 4 flip-flops = 8(F٤J١٠KE
3Q
Repeat Sequence
אאאJאא ١٤٧ א א
אאאא א אא
- ١٣٣ -
٤J١٠אאאCountersאאאאאאאאאא
אKאאא)binary bits(،אאאאאאאא
אא)clock input(Kאאאאאאאאאאאאאאא
אאKאאאאאאאא
)Asynchronous Counters(אאאאאא )Synchronous Counters(Kאאאאאאאאאאאא
אאKאאאאאאאא،אאאאאאאא)Master Clock(K
،אאאאאאאאאאאאאאאאאK
٤J١٠J١אאאאאאאAsynchronous Binary-Up Counters ٤J٣٢FEאאאK
J-KאאKאאאאאאאאאאאK
אJ,Kא)High(،אא)Toggle()Negative edge(אאK
אאאאאאא)Q(א٤J٣٢FKEאQ3,Q2,Q1,Q0אא)4-bit word(א
אא0000אאאאאאאF٤J١١KEאאFF0
)Q0()LSB(אאFF3)Q3(א)MSB(K
אאא ١٤٧ א א
אאאא א
- ١٣٤ -
F٤J٣٢EאאאאK
אא)FF0(אאא)Clock input(،אQ0)Toggle (،אאא
אQ0٤J٣٢FKEאאאאאאQ0"0""1"אאא"1""0"אKא
אQ0אאאFF1،Q0אQ1)Toggle(KQ1א
Q2،Q2אQ3K
Q0
Q1
Q2
Q3
0 0 0 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FE
CK
0Q 1Q2Q 3Q
FF0 FF1
CK CK CKClockInput
0Q1Q 2Q 3Q
K K K K
J J J J
FE
FF2 FF3
אאא ١٤٧ א א
אאאא א
- ١٣٥ -
אא אQ0 Q1 Q2 Q3
0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 0 4 0 0 1 0 5 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 1 9 1 0 0 1
10 0 1 0 1 11 1 1 0 1 12 0 0 1 1 13 1 0 1 1 14 0 1 1 1 15 1 1 1 1
F٤J١١EאאאאאK
•אThe Maximum Count (N) of a Counter אאאF٤J١١Eאאא،
אאא0001]א)1(אא[אאאא،0010א]2(א(אא[אאאאא،0011]
)3(אא[א،Kאאאאאאאא،אאאאW
1 2N n −=W = Nאאא (N = maximum count before cycle repeats) = nאאאאא(n = number of flip-flops in the counter circuit)
Cycle Repeats
Binary Count
אאא ١٤٧ א א
אאאא א
- ١٣٦ -
אאאא٤J٣٢FEאW
)1111(15 116 12
12N
210
4
n
=−=−=
−=
•אאאThe Modulus (MOD) of a counter אאא)Modulus of a counter()MOD(א
אאאKאא٤אJ٣٢FEMOD(16)אא(16)00001111א
F٤J١١KEMODאאאW
MOD = 2n MOD = modulus of the counter n = number of flip-flops in the counter circuit
אאאא٤J٣٢FEאאאאאW
162
2MOD4
n
==
=
•אאThe Frequency Division of a counter
אאאאא٤J٣٢FEאא)frequency divider(אאאאאאא2،אא
אא2Kא2،א2אא2،א
אאאאאא4٤J٣٢FEאאאא
אQ1 K،אאאאא2،
אאא ١٤٧ א א
אאאא א
- ١٣٧ -
אאא4אא،8א،16אKאאאאאאW
Division Factor = 2n FאE N = number of flip-flops in the counter circuit
•אאThe Propagation Delay Time (tp) of a counter
אאאאאא)Ripple counter(אא،אא،אאאאK
،אאאאאאאאאאאאK
،אאאFאאאEאאאא01111000Kאא
0111אא)tp(ns10ns40) 4 Flip-Flops × 10ns (א1000Kא)counting speed(אא
אאאאאאאKאאאאאW
p
9
t n 10 1f××
=
Wf = upper clock pulse frequency limit n = number of flip-flops in the counter circuit tp= propagation delay time of each flip-flop in nanoseconds
٤J١٠J٢אאאאאאאAsynchronous Binary Down Counters
אאאאאאאאא"1"Kאאאאאאאאא
א"1"אK٤אJ٣٣FEא
אאא ١٤٧ א א
אאאא א
- ١٣٨ -
אאאאJ-KKאQאאQאאאK
אאאQאאא٤J٣٣FKEאאאאא(RESET)Q3,Q2,Q1,Q0
0000KאאאאQLowאQ1111KאאאאאאFF3,FF2,FF1HighKאאJ,KאאאHighא
)Toggle(אאאK
F٤J٣٣EאאאאK
אאאאאאFF0،אQ0"0""1"אא،0Q"1""0"אא
CK
0Q1Q 2Q 3
Q
FF0 FF1 FF2 FF3
CK CK CKClockInput
0Q
1Q
2Q 3Q
K K K K
HIGH
FE
ClockInput
Q0
Q1
Q2
Q3
0 0 0 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FE
0Q
1Q2
Q 3Q
J J J J
אאא ١٤٧ א א
אאאא א
- ١٣٩ -
אאFF1א،Q1"1""0"א1Q"1""0"Kאא1Q"1""0"אFF2،
Kא
אא אQ0 Q1 Q2 Q3
15 1 1 1 1 14 0 1 1 1 13 1 0 1 1 12 0 0 1 1 11 1 1 0 1 10 0 1 0 1 9 1 0 0 1 8 0 0 0 1 7 1 1 1 0 6 0 1 1 0 5 1 0 1 0 4 0 0 1 0 3 1 1 0 0 2 0 1 0 0 1 1 0 0 0 0 0 0 0 0
F٤J١٢EאאאאאK
אאאאאאQ3,Q2,Q1,Q0(15)10 = 1111אאאF٤J١٢KEאאאא
אאאאאKא٤אJ٣٣FEאא، FF0
،אאאQ0א،אQ3,Q2,Q1אאאאאאK
Cycle Repeats
Binary Count
אאא ١٤٧ א א
אאאא א
- ١٤٠ -
٤J١٠J٣אאאאאLאאאAsynchronous Binary Up/Down Counters
אאאא،אאאאאאאאאאאאאאאאQ
אאאאאאאאאQKF٤J٣٤EאL
AND-ORאאDOWNUP /K
F٤J٣٤EאאאאK
אאDOWNUP /אHigh،אאANDא
א)Enabled(،Qאאאאאא،אאא،א
DOWNUP /אLow،אאאאאא)Disabled(אאאאאא)Enabled(
Qאאאאאא،אאK
ClockInput
0Q
HIGH
CK
0QFF0
0Q
1QFF1
CK
1Q
1Q
2QFF2
CK
2Q
2Q
3Q
FF3
CK
3Q
3QK K K K
UP/DOWN control
J J J J
אאא ١٤٧ א א
אאאא א
- ١٤١ -
٤J١٠J٤אאאאאאAsynchronous Decade (MOD-10) Counters ٤J٣٥FEאאאאאאאאא)MOD-10(K
F٤J٣٥EאאאאK
אאא0000F0E1001F9Eא
אא٤J٣٥FEאאF٤J١٣KE
HIGH
CK
0Q 1Q
2Q 3Q
FF0 FF1 FF2 FF3
CK CK CKClockInput
0Q1
Q2
Q3
Q
K K K K
FE
ClockInput
Q0
Q1
Q2
Q3
0 0 0 0
1 2 3 4 5 6 7 8 9 10
FE
CLR
CLR CLR CLR CLR
J J J J
אאא ١٤٧ א א
אאאא א
- ١٤٢ -
אאאאא 10101111F10אא15EאNAND אאאאFCLREאא
אKאאאQ1אאQ3Kאא1010אF10אאEQ3,Q1אHigh،
אNANDLow )CLEAR (אKאא٤J٣٥FEאCLR)inactive(א
00001001KאאאאQ3,Q1אHighKאאQ1،Q3،)CLEAR(אאאא
אאCLRKאאאאאF٤J١٣Eאא،אא0א9אK
אא אQ0 Q1 Q2 Q3
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F٤J١٣EאאאאאK
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אאאא א
- ١٤٣ -
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0Q 1Q
2Q 3Q
FF0 FF1 FF2 FF3
CK CK CK
ClockInput
0Q
1Q
2Q
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K K K K
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J J J J
CK
אאא ١٤٧ א א
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- ١٤٤ -
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אאא ١٤٧ א א
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- ١٤٥ -
אאא ١٤٧ א א
אאאא א
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CK
S
R
CK
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אאא ١٤٧ א א
אאאא א
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CK
J
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אא א
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אא ١٤٧ א א
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- ١٥٠ -
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F٥J١EאאANDאF٥J١KE
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×
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BA
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A B
A A B B0
1
2
3
Inputs
Outputs
אא ١٤٧ א א
אא א
- ١٥١ -
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אאאKF٥J٢EאאF٥J١EאאאK
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F٥J٢EאאPLDK
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×
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×
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BA
BA
BA
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0123 QQQQ
A B
A A B B
0
1
2
3
Inputs
Outputs
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אא ١٤٧ א א
אא א
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0
1
2
3
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AB = 00 AB = 10K
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Q0 Q1 Q2 Q3 B A
1 1 0 0 0 0 BA
0 0 1 1 1 0 BA
1 0 0 0 0 1 BA
0 0 1 0 1 1 AB
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אא ١٤٧ א א
אא א
- ١٥٤ -
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F٥J٤EאאPLDK
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אא ١٤٧ א א
אא א
- ١٥٥ -
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× × ××× ×× ×× ×× ×× × ×× × ××× × ×× × ××× × ××× × ××× × ××× × ××× × ××
××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××
I3 I2 I1 I0
O3 O2 O1 O0
×
×
אא ١٤٧ א א
אא א
- ١٥٦ -
אPLAאאאאאא،אK
F٥J٦EאאאPALK
OR
AND
××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××
O3 O2 O1 O0
I3 I2 I1 I0
אא ١٤٧ א א
אא א
- ١٥٧ -
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Erasable Programmable Logic Device (EPLD) אאא)PLDs(א
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×
אא ١٤٧ א א
אא א
- ١٥٨ -
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אK
א א
Q0 Q1 Q2 Q3 B A
1 1 1 0 0 0
0 0 1 1 1 0
1 0 1 0 0 1
0 0 0 1 1 1
٢EאאאאאQ0,Q3אאאK
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א ١٤٧ א א
א
א
אא
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١J١ ٢١J٢אאא ٣ ١J٣אאא ٤ ١J٤אאאאא ٦ ١J٤J١אאאאאא ٦ ١J٤J٢אאאאא ٧ ١J٥אאאאא ٩ ١J٦אאאא ١٠ ١J٦J١אא ١٠ ١J٦J٢אא ١٠ ١J٧אאאאא ١١ ١J٨אאאא ١٢ ١J٨J١אא ١٣ ١J٨J٢אא ١٣ ١J٨J٣אא ١٤ ١J٩אאאאאא ١٤
١J١٠אאא ١٥ ١J١٠J١אאאא ١٥ ١J١٠J٢אאאא ١٦ ١J١٠J٢J١אאאאאא ١٦
א ١٤٧ א א
א
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١J١٠J٦אאא٢٠ א ١J١٠J٦J١אא ٢٠ ١J١٠J٦J٢אאא ٢٢ ١J١١אאאא ٢٣ ١J١١J١אאאא ٢٣ ١J١١J٢אאאא ٢٣ ١J١١J٢J١אאאאא
אא ٢٣
١J١١J٢J٢אאאאאא ٢٤ ١J١١J٣אאאא ٢٥ ١J١١J٤אאאאא ٢٦ ١J١١J٥אאאא٢٧ א ١J١١J٦אאאאא ٢٨ ١J١١J٧אאאאא ٢٩ ١J١١J٨אאאאא ٢٩ ١J١١J٨J١אאאא ٢٩ ١J١١J٨J٢אאאא ٣٠
א ١٤٧ א א
א
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אאא٣٥ ٢J١ ٣٦ ٢J٢אא٣٦ ٢J٣א AND٣٧ ٢J٤ א OR٤٠ ٢J٥א NOT FאE ٤٢ ٢J٦א NAND ٤٢ ٢J٧א NOR ٤٤ ٢J٨א OR אFאE٤٥ ٢J٩א NOR אFאE٤٧ ٢Jא١٠אא٤٨ ٢J١١אאא٥٠ ٢J١٢אאאא٥١ ٢J١٣אא٥٢ ٢J١٤אאא٥٤ ٢J١٥אאאאאא٥٥
٥٨ אאWאאאאא
אאא٦١ ٣J١٦٢ ٢J٣٦٢ ٣J٣אאאאNOR , NAND٦٤ ٣J٣J١אאNAND٦٥
א ١٤٧ א א
א
٣J٣Jא٢אNOR٦٦ ٣J٤אאאאאאאNAND،
NOR٦٧
٣J٤J١אאאNAND٦٧ ٣J٤J٢אאאNOR٦٩ ٣J٥٧٢ ٣J٦אאא٧٣ ٣J٧אאאא٨١ ٣J٧J١אאא٨١ ٣J٧J٢אאא٨٢ ٣J٧J٣אאא٨٥ ٣J٧J٤אאא٨٧
٩٠
אאאWאאאא
אאא٩٢ ٤J١٩٣ ٤J٢א٩٣ ٤J٣אS-Rאא٩٨ ٤J٤אאאD ١٠١ ٤J٥אJ-Kאא١٠٣ ٤J٦אאאT ١٠٥ ٤J٧א–א١٠٦ ٤J٨אא١١٤ ٤J٨Jא١אאאא١١٤ ٤J٨J٢אאאאאא١١٥
א ١٤٧ א א
א
٤J٨J٣אא555١١٦ ٤J٨J٣J١א555אאאא١١٦ ٤J٨J٣J٢אאאאאא١١٩ ٤J٩אא١٢١ ٤J٩J١א١٢٢ ٤J٩J٢אא١٢٤ ٤J٩J٢J١אאאא–אא١٢٥ ٤J٩J٢J٢אאא–אא١٢٧ ٤J٩J٢J٣אאא–אא١٢٨ ٤J٩J٢J٤אאאFאE١٢٩ ٤J٩J٢J٥א١٣١ ٤J١٠אאא١٣٣ ٤J١٠J١אאאאאאא١٣٣ ٤J١٠J٢אאאאאאא١٣٧ ٤J١٠J٣אאאאאLאאא١٤٠ ٤J١٠J٤אאאאאא١٤١ ٤J١٠J٥אאאאאאא١٤٣ ٤J١٠J٦ אאאאאא١٤٤
١٤٦ אאWאא
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א ١٤٧ א א
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