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● CPLD 基础知识. ● MAX+PLUSSII 简介. ● VHDL 语言. 兰州石化职业技术学院电子系. CPLD 技术应用. EDA 技术应用. 第 1 讲 前言及可编程逻辑器件. 使用对象: 专用集成电路 ASIC 的芯片设计研发人员 广大的电子线路设计人员 电子设计自动化 EDA ( Electronic Design Automation )技术是以大规模 可编程逻辑器件 为设计载体,通过 硬件描述语言 设计, EDA 软件 编译、仿真,最终 下载 到设计载体中,从而完成系统电路设计任务的新一代设计技术。. 一、前言. - PowerPoint PPT Presentation

Text of ● CPLD 基础知识

  • CPLD MAX+PLUSSII VHDL

  • EDA 1

  • ASIC

    EDAElectronic Design AutomationEDA

  • EDA EDAEDA2070CAD2080CAED2090EDA

  • PCBAccelTango 2070CAD

  • EDAorCADProtel EDA2080(CAED)

  • 2090SOCSystem on a Chip,EDAEDAEDA2090(EDA)

  • EDA

  • PLDPLDCPU,74PLDPLD PLD

  • 2.1

  • 2.2 -SPLDCPLDFPGA

  • 2.3 PLD-

    _1092499859.vsd

  • 2.3 PLD

  • 1 2.3 PLD

  • 2 2.3 PLD

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  • 6 2.3 PLD

  • 2.3 PLD

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  • 2.4 PROMProgrammable Read Only MemoryEPROMEEROMPLAProgrammable Logic ArrayPALProgrammable Array LogicGALGeneric Array Logic

  • 4SPLD 2.4

    PROMPLAPALGAL

  • 1PROMPLD PROM 2.4

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  • 2PLA 2.4

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  • PLA PROM 2.4

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    K

    D

    L

    S

    R

    1

    J

    OLMC

    S

    J

    OLMC

    S

    J

    OLMC

    S

    OLMC

    OLMC

    1

    OLMC

    OLMC

    OLMC

    1

    2

    I

    I

    0

    7

    19

    I/O/Q

    CLK

    0 3

    4 7

    8

    12

    11

    15

    16

    19

    20

    23

    24

    27

    28

    31

    1

    I/CLK

    I

    3

    I

    I

    8

    15

    18

    I/O/Q

    OE

    4

    I

    I

    16

    23

    17

    I/O/Q

    5

    I

    I/OE

    24

    31

    16

    I/O/Q

    6

    I/O/Q

    I/O/Q

    32

    39

    15

    I/O/Q

    7

    I/O/Q

    40

    47

    14

    8

    48

    55

    13

    9

    56

    63

    12

    11

    Vcc

    SG1

    SL0

    7

    SL1

    7

    SG0

    SL0

    6

    19

    I/O

    7

    Vcc

    SG1

    1

    SL0

    6

    SL1

    6

    SG1

    SL0

    6

    18

    I/O

    6

    CLK/I

    0

    2

    I

    1

    3

    I

    2

    0

    7

    8

    15

    0 3

    4 7

    8

    12

    16

    20

    24

    28

    11

    15

    19

    23

    27

    31

  • 3 PAL 2.4

  • General Array Logic Device

    GALPALOLMCOLMC832EEPROMPAL4 GAL 2.4

  • /GAL16V8

  • OLMC GAL16V8

  • 2.4 LATTICEispLSI 1032ispLSI 1032ispLSI 10005V1. ispLSI 10326000192CMOSEEPROM8464I/O8 fmax = 125 MHz

  • 2. ispLSI 10322.4 LATTICEispLSI 1032

  • 3. ispLSI 10322.4.1 LATTICEispLSI 1032

  • 1) GRPGlobal Routing Pool2.4 LATTICEispLSI 1032

  • 2) GLBGeneric Logic BlockGLBGRP8322.4 LATTICEispLSI 1032

  • GLBGLB2.4 LATTICEispLSI 1032

  • GLBGLB1816GRP2I/OGLB20204442.4 LATTICEispLSI 1032

  • 3) IOCInput Output CellIOC64IN0 ~ IN63I/O2.4 LATTICEispLSI 1032

  • 4) ORPOutput Routing PoolORPGLBIOCORP8GLB32ORP1616IOCORPGLB16I/OORP16GRPI/OGLBORPI/OGLB2.4 LATTICEispLSI 1032

  • CDNClock Distribution networkCDNY0Y1Y2Y4CDNCLK0CLK1CLK2GLBIOCLK0IOCLK1I/OGLBB0CDN

  • 6) MegablockispLSI 1032 8GLBORPIOC 2GLBispLSI 1032 42.4 LATTICEispLSI 1032

  • 2.5.1 FPGA-----Field Programmable Gate Array12SRAM3I/OPALGAL45CLBI/O6Look-Up-Table) 2.5 FPGA

  • Look-Up-Table)LUTLUTRAM FPGA4LUTLUT416x1RAM HDLPLD/FPGARAM, 2.5.1 FPGA

    LUT

    1

    2

    3

    4

  • 2.5.1 FPGA

  • Fabcd2.5.1 FPGA

  • 2.6 CPLD CPLD-----Complex Programmable Logic Device12CMOS EPROMEEPROMFLASHSRAM3I/OPALGAL4 56PALGAL7Product-Term)PLD

  • 2.6.1 FLEX 10KFPGA

  • (1) LABLE

  • (2) LE2.6.1 FLEX 10KFPGALAB

  • PLD/FPGA ICPLD/FPGACPLD/FPGA ALTERAXILINXLatticeALTERAXILINX60%

  • MAX3000/7000,FLEX10K,APEX20KACEX1KStratixCyclone MaxPlusII,QuartusII Altera

  • FPGAFPGA XC9500Coolrunner Spartan, Virtex ISE XilinxALTERA PLD/FPGA60%AlteraXilinx AlteraXilinxPLD XILINX

  • LatticeISP,ISPPLDALTERAXILINXPLD 199999VantisAMD,200112agereLucentFPGA LatticePLD ispMACH4000PLDLatticeEC/ECPFPGAispPAC ispSynario,ispLeverLattice

  • Lattice

  • 708090PROM PLA PLA GALFPGAEPLD CPLDSoPC