Bao Cao Thuc Tap Pic18f4520

Trng i Hc Cng Nghip H Ni

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BO CO THC TP TI : Tm hiu v truyn thng ni tip trong vi iu khin pic18f4520 v thit k modul th nghim.I. Tng quan v vi iu khin pic18f4520 B vi iu khin ghi tt l Micro-controller l mch tch hp trn mt chip c th lp trnh c, dng iu khin hot ng ca h thng. Theo cc tp lnh ca ngi lp trnh, b vi iu khin tin hnh c, lu tr thng tin, x l thng tin, o thi gian v tin hnh ng m mt c cu no . Trong cc thit b in v in t cc b vi iu khin iu khin hot ng ca ti vi, my git, u c lase, l vi ba, in thoi Trong h thng sn xut t ng, b vi iu khin s dng trong robot, cc h thng o lng gim st .Cc h thng cng thng minh th vai tr ca vi iu khin ngy cng quan trng. Hin nay trn th trng c rt nhiu h vi iu khin nh: 6811 ca Motorola, 8051 ca Intel, Z8 ca Zilog, PIC ca Microchip Technology Trong ti ny nghin cu v pic18f4520 v n c nhiu u im hn cc loi vi iu khin cc nh : ADC 10 BT, PWM 10 BT, EEPROM 256 BYTE, COMPARATER, ngoi ra n cn c cc trng i hc trn th gii c bit l cc nc Chu u hu ht xem PIC l 1 mn hc trong b mn vi diu khin ni vy cc bn cng thy s ph bin rng ri ca n. Ngoi ra PIC cn c rt nhiu nh sn xuat phn mm to ra cc ngn ng h tr cho vic lp trnh ngoi ngn ng Asembly nh :MPLAB, CCSC, HTPIC, MIRKROBASIC, Hin nay c kh nhiu dng PIC v c rt nhiu khc bit v phn cng, nhng chng ta c th im qua mt vi nt nh sau :

8/16 bt CPU, xy dng theo kin trc trn kin trc Harvard sa i, vi tp lnh rt gn (do vy PIC thuc loi RISC).


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Flash v Rom c th tu chn 256 byte n 256 kbybe Cc cng xut/nhp (mc lgic thng t 0v n 5v, ng vi mc logic 0 v 1)

8/16 bt timer

Cc chun giao tip ngoi vi ni tip ng b/ khng ng b B chuyn i ADC B so snh in p MSSP Pripheral dng cho cc giao tip I2C, SPI B nh ni EEPROM - c th ghi/ xo ln ti hng triu ln Modul iu khin ng c, c encoder H tr giao tip USB H tr iu khin Ethernet H tr giao tip CAN H tr giao tip LIN H tr giao tip IRDA DSP nhng tnh nng x l tn hiu s

1. S chn vi iu khin pic18f4520


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2. Cc thng s v vi iu khin pic18f4520

CPU tc cao c 75 cu trc lnh, nu c cho php c th ko di n 83 cu trc lnh. Hu ht cc cu trc lnh ch mt mt chu k my, ngoi tr lnh r nhnh chng trnh mt hai chu k my Tc lm vic: xung clock n 40MHz, tc thc thi lnh 125ns B nh chng trnh ( flash program memory) l 32kbyte B nh d liu SRAM l 1536 byte


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B nh d liu EEPROM l 256 byte 5 port Vo hoc ra

4 b timer 1 capture/compare/PWM modules

1 enhanced capture/ compare/PWM modules

Giao tip ni tip : MSSP, enhanced USART. Cng giao tip song song. 13 b Analog to Digital module 10 bt POR,BOR Bn cnh l mt vi c tnh khc ca vi iu khin nh: + B nh Flash c kh nng ghi xo c 100.000 ln. + B nh EEPROM vi kh nng ghi xo c 1.000.000 ln. + Flash/D liu b nh EEPROM c th lu tr hng 100 nm. + Kh nng t np chng trnh vi s iu khin ca phn mm. + Watchdog timer vi b dao ng trong. + Chc nng bo mt m chng trnh . + Ch SLEEP. + C th hot ng vi nhiu dng Oscillator khc nhau.


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3. S khi ca vi iu khin pic18f4520


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4. S khi b nh d liu pic18f4520

II. Truyn thng ni tip


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1. gii thiu CH SYNCHRONOUS SERIAL PORT (MSSP) MODULE - SPI - I2C ENHANCED UNIVERSAL SYNCHRONOUS RECEIVER RANSMITTER (EUSART) 2. Tng quan v khi MSSP MSSP l khi giao din ng b ni tip, c s dng giao tip vi cc thit b ngoi vi khc hoc cc vi iu khin khc. Cc thit b ngoi vi nh l EFPROM, thanh ghi dch, iu khin hin th, cc khi chuyn i A/D, . . . Cc ch hot ng ca MSSP : + Ch SPI + Ch I2C Trong ch I2C phn cng h tr cc ch sau : + Ch ch. + Ch a ch. + Ch t. Thanh ghi iu khin Khi MSSP c 3 thanh ghi lin quan n l : thanh ghi trng thi (SSPSTAT), v 2 thanh ghi iu khin (SSPCON1 v SSPCON2 ). Thit lp cc thanh ghi xc nh ch lm vic ca khi MSSP l SPI hoc I2C. 2.1 SPI Ch SPI cho php 8 bt d liu c truyn v nhn ng thi. Tt c 4 ch ca khi SPI u c h tr. C 3 chn in hnh cho chun giao tip ny : + Ng ra d liu dng ni tip RC5/SDO. + Ng vo d liu dng ni tip RC4/SDI/SDA. + xung ng b ni tip RC3/SCK/SCL. 2.1.1 Gii thiu v giao tip SPI


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Trong ch t chn th 4 c th c s dng iu khin l : Chn chn i tng giao tip : RA5/AN4/ SS /HLVDIN/C2OUT.

Hnh 1: Biu din s khi ca khi MSSP khi iu khin trong khi SPI 2.1.2 Khi to ch SPI Khi khi to ch SPI ta cn thit t cho cc bt SSPCON v SSPSTAT cho php cc ch hot ng v cc c tnh trong ch SPI, l : + Ch ch + Ch t + Cc tnh xung clock + Pha ly mu d liu vo + Sn xung clock + Xung nhip ( ch c trong ch ch )


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+ La chn ch t (ch c trong ch t ) MSSP bao gm thanh ghi dch truyn nhn (SSPSR) v thanh ghi m (SSPBUF) , SSPSR dng dch d liu vo v ra, u tin l bt msb. Khi qu trnh nhn d liu sn sng, d liu s c ghi vo SSPSR sau d liu s c gi SSPBUF. Khi pht hin b m y c BF (SSPSTAT) v bt cho php ngt c t ln. B m d liu 2 lp cho php nhn tip 1 byte d liu trc khi c. bt k s ghi no ti thanh ghi SSPBUF trong thi gian truyn nhn d liu s b l i v bt pht hin xung t WCOL (SSPCON1) s c t ln. Bt WCOL phi c xa bng phn mm xc nh vic ghi tip theo ln thanh ghi SSPBUF. SSPSR khng th c hoc ghi trc tip m ch c th truy cp thng qua thanh ghi SSPBUF. 2.1.3 Thanh ghi Khi MSSP c 4 thanh ghi iu khin khi hot ng ch SPI : + Thanh ghi iu khin 1 ( SSPCON1) + Thanh ghi trng thi ( SSPSTAT ) + Thanh ghi m truyn hoc nhn (SSPBUF) + Thanh ghi dch d liu ( SSPSR) ( khng trc tip iu khin c ) SSPCON1 v SSPSTAT l thanh ghi iu khin v thanh ghi trng thi trong ch SPI. Thanh ghi SSPCON1 c th c v ghi. 6 bt di ca thanh ghi SSPSTAT ch c th c, 2 bt trn c th c v ghi. Hnh 2 SSPSTAT : Thanh ghi trng thi (ch SPI )

Bt 7

SMP : bt ly mu SPI ch ch : 1= ly mu d liu vo thi im cui ca d liu ra.


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0= ly mu d liu vo thi im gia ca d liu ra. SPI ch t : SMP phi c xa khi SPI c s dng ch t. Bt 6 CKE : bt chn xung clock 1= Truyn khi xut hin s chuyn tip t tch cc n trng thi ngh. 0= Truyn khi xut hin s chuyn tip t trng thi ngh ln tch cc. Bt 5 Bt 4 Bt 3 Bt 2 Bt 1 Bt 0 D/ A : D liu hoc a ch Ch s dng trong ch I2C . P : bt stop Ch s dng trong ch I2C. S : bt bt u Ch s dng trong ch I2C. R/ W : c hoc ghi thng tin Ch s dng trong ch I2C. UA : bt cp nht a ch Ch s dng trong ch I2C. BF : bt trng thi bo y b m ( duy nht ch truyn ) 1= Truyn hon tt ( SSPBUF y ) 0= Truyn khng hon tt ( SSPBUF rng)

Hnh 3

SSPCON1 : Thanh ghi iu khin khi MSSP (trong ch SPI)


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Bt 7

WCOL : bt pht hin xung t khi ghi 1= Thanh ghi SSPxBUF c ghi trong khi vn c s truyn t trc. 0= khng c xung t.

Bt 6

SSPOV : bt c trn nhn SPI ch t : 1= 1 byte c nhn trong khi d liu c vn cn trong thanh ghi SSPBUF. Trong trng hp ny d liu trong SSPSR b ghi ln. Trn ch xut hin duy nht trong ch t. Ngi s dng phi c SSPBUF d liu truyn l duy nht, trnh c trn c t ln.( c trn phi xa bng phn mm). 0= khng c s trn xy ra.

Bt 5

SSPEN : bt cho php truyn thng ni tip 1= cho php cng ni tip v thit lp SCK, SDO, SDI, v chn ca cng ni tip. 0= khng cho php cng ni tip v thit lp cc chn nh l chn vo hoc ra.S S

nh l cc

Bt 4

CKP : bt chn cc tnh xung clock. 1= trng thi ngh khi xung mc cao. 0= trng thi ngh khi xung mc thp.

Bt 3

SSPM3 : SSPM0 : cc bt chn ch 0101= SPI ch t (SCK l chn xung clock, ng,S SS S

khng cho php hot cho php hot ng).

s dng nh chn vo hoc ra ).S S

0100= SPI ch t (SCK l chn xung clock, 0010 : SPI ch ch (xung clock = Fosc/64).

0011 : SPI ch ch ( xung clock = u ra TMR2/2 ).


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0001 : SPI ch ch ( xung clock =Fosc /16). 0000 : SPI ch ch (xung clock =Fosc/4). 2.1.4 Cho php SPI vo hoc ra Thit lp thanh ghi SSPCON v bt SSPEN ( SSPCON1) c t ln cho php cng ni tip. Vic thit lp ny cho php SDI, SDO, SCK, trong thanh ghi trisc : + SDI : t ng iu khin bi khi SPI + SDO : xa bt th 5 trong thanh ghi TRISC + SCK : (ch ch ) phi xa bt th 3 trong thanh ghi TRISC + SCK : (ch t ) phi t bt th 3 trong thanh ghi TRISC. +S S

S S

l cc

chn ca cng ni tip. Xc nh hng d liu ca cc chn ny c thit lp

: phi t bt th 5 trong thanh ghi TRISC

S kt ni in hnh :

Hinh 4 s kt ni SPI ch hoc t Hnh 4 biu din s kt ni gia 2 vi iu khin. Vi iu khin ch (processor 1) khi to qu trnh truyn d liu bng vic gi tn hiu xung ng b SCK. D liu s c dch t c hai thanh ghi SSPSR a ra ngoi nu c mt cnh ca xung ng b tc ng v ngng dch khi c tc ng ca cnh cn li. C hai khi


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ch v t nn c n nh chung cc quy tc tc ng ca xung clock ng b d liu c th dch chuyn ng thi. 2.1.5 Ch ch Vi iu khin ch c th khi to qu trnh truyn d liu bt c thi im no bi v n iu khin xung ng b SCK. Trong ch ch, d liu c truyn/nhn ngay khi thanh ghi SSPSR c ghi ln. Nu ch cn nhn d liu, lc ny chn SDO khng c tc dng ta c th n nh n l ng vo ( t bt TRISC), d liu s c dch vo thanh ghi SSPSR theo mt tc c nh sn cho xung clock. Sau khi nhn c 1 byte d liu hon chnh, byte d liu s c a vo thanh ghi SSPBUF, bt BF c t v ngt xy ra. Trong ch ch, tc ca xung ng b clock c chn : + Fosc/4 + Fosc/16 + Fosc/64 + u ra timer2/2 iu ny cho php tc ti a truyn d liu 40 MHZ hoc 10000 Mbps.


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Hnh 5 Gin xung ca ch ch v cc tc ng ca cc bt iu khin 2.1.6 Ch t Trong ch ny, d liu c truyn v nhn khi c xung ng b bn ngoi xut hin chn SCK. Khi nhn 8 bt th c ngt SSPIF c t ln.


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Trc khi cho php khi SPI ch t th ng xung clock phi trng thi ngh (idle), ta c th quan st ng ny bng vic quan st qu trnh c ti chn SCK. Trng thi idle c xc nh bi bt CKP ( SSPCON1 ). Ch ny hot ng ngay c khi vi iu khin ang ch ng. Ngt truyn nhn cho php nh thc vi iu khin

Hnh 6 Gin xung chun giao tip SPI ( ch t ) 2.1.7 Tm lc + Thanh ghi INTCON : Cha bt cho php ngt ton cc (GIE V PEIE ) + Thanh ghi PIR1 + Thanh ghi PIE1 + Thanh ghi IPR1 + Thanh ghi TRISA + Thanh ghi TRISC : Cha bt SSPIF : Cha bt SSPIE : Cha bt SSPIP : iu khin xut nhp chn RA4/AN4/ SS /HLVDIN/C2OUT : iu khin xut nhp PORTC.


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+ Thanh ghi SSPBUF

: Thanh ghi m d liu

+ Thanh ghi SSPCON1 : iu khin chun giao tip SPI + Thanh ghi SSPSTAT : Cha cc bt ch th trng thi chun giao tip SPI 2.2 I2C 2.2.1 Gii thiu v giao tip I2C y l mt ch khc ca khi MSSP. Chun giao tip I2C cng c Ch ch , t v cng c kt ni vi ngt. Chun giao tip I2C s dng 2 chn truyn nhn d liu : + RC3/SCK/SCL : Chn truyn dn ni tip xung clock + RC4/SDI/SDA : Chn truyn dn ni tip d liu

Hnh 7 : S khi MSSP ( Ch I2C ) 2.2.2 Cc ch hot ng


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Khi MSSP c cho php bi bt SSPEN (SSPCON1). Giao tip I2C c nhiu ch hot ng v c iu khin bi cc bt SSPCON1 bao gm : + I2C ch ch, xung clock = (Fosc/4 )*(SSPADD+1). + I2C ch t, 7 bt a ch. + I2C ch t, 10 bt a ch. + I2C ch t, 7 bt a ch, cho php ngt khi pht hin bt start v stop . + I2C ch t, 10 bt a ch, cho php ngt khi pht hin bt start v stop . + I2C iu khin ch ch bng phn mm, ch t th khng c ch ny. La chn ch I2C v t bt SSPEN, cc chn SCL v SDA s trng thi cc thu h. Do phi ko in tr ngoi, ng thi cn thit t cc gi tr ph hp cho cc bt trong thanh ghi TRISC i vi cc chn SDA v SCL. 2.2.3 Thanh ghi Khi MSSP c 6 thanh ghi iu khin ch I2C. Cc thanh ghi l : + Thanh ghi iu khin MSSP 1 (SSPCON1) + Thanh ghi iu khin MSSP 2 (SSPCON2) + Thanh ghi trng thi MSSP (SSPSTAT) + Thanh ghi m truyn nhn ni tip (SSPBUF) + Thanh ghi dch MSSP (SSPSR) (khng trc tip truy cp). + Thanh ghi a ch MSSP (SSPADD) Cc thanh ghi iu khin SSPCON1 v SSPCON2 c th c v ghi. Thanh ghi SSPSTAT ch cho php c v ghi 2 bt u, 6 bt cn li ch cho php c. Thanh ghi SSPBUF cha d liu s c truyn i hoc nhn c v ng vai tr nh mt thanh ghi m cho thanh ghi dch d liu SSPSR. Thanh ghi SSPSR khng th truy xut trc tip c, mun truy xut n ta phi thng qua thanh ghi SSPBUF. Thanh ghi SSPADD cha a ch ca thit b ngoi vi cn truy xut d liu ca I2C khi hot ng ch t. Khi hot ng ch ch, thanh ghi SSPADD cha gi tr to ra tc baud cho xung clock dng truyn nhn d liu.


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Trong qu trnh nhn d liu, c 2 thanh ghi SSPSR v SSPBUF to thnh b m nhn d liu 2 lp. khi SSPSR thc hin nhn 1 byte hon tt, n s ghi ti thanh ghi SSPBUF v c ngt SSPIF c t. Trong qu trnh truyn, chng khng ng vai tr l b m d liu 2 lp. Khi ghi ti SSPBUF lc ny s ghi ti c SSPBUF v SSPSR. Hnh 8 SSPSTAT : Thanh ghi trng thi MSSP(ch I2C)

Bt 7

SMP : bt iu khin tc Trong ch ch hoc ch t : 1= khng iu khin tc , ch tc chun (100 KHZ v 1MHZ ). 0= cho php iu khin tc , tc cao (400 KHZ)

Bt 6

CKE : bt chn SMBUS Trong ch ch hoc ch t : 1= cho php u vo SMBUS 0= khng cho php u vo SMBUS

Bt 5

D/ A bt d liu hoc bt a ch Trong ch ch : Dng d ch. Trong ch t : 1= byte cui ca qu trnh truyn hoc nhn l d liu. 0= byte cui ca qu trnh truyn hoc nhn l a ch.

Bt 4

P : bt stop 1= xc nh bt stop 0= khng xc nh bt stop

Bt 3

S : bt start 1= pht hin bt start


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0= khng pht hin bt start Bt 2 R/ W : c hoc ghi thng tin Trong ch t : 1= c. 0= ghi. Trong ch ch : 1= cho php truyn. 0= khng cho php truyn. Bt 1 UA : bt cp nht a ch ( ch t 10 bt ) 1= cp nht a ch vo thanh ghi SSPADD 0= khng cp nht a ch Bt 0 BF : bt bo trng thi y b m Trong ch truyn : 1= SSPBUF y. 0= SSPBUF rng. Trong ch nhn : 1= SSPBUF y ( khng bao gm 0= SSPBUF rng ( khng bao gm Hnh 9AK CAK C

v bt stop ). v bt stop ).

SSPCON1 : Thanh ghi iu khin 1 (ch I2C)

Bt 7

WCOL : bt pht hin xung t lc ghi Truyn trong ch ch : 1= d liu truyn c a vo thanh ghi SSPBUF trong khi ch truyn d liu ca I2C cha sn sng. 0= khng c s xung t. Truyn trong ch t :


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1= d liu mi c a vo thanh ghi SSPBUF trong khi cha truyn xong d liu c. 0= khng c s xung t. Trong ch nhn (ch ch hoc t ) : Khng s dng n bt ny. Bt 6 SSPOV : bt c trn nhn Ch nhn : 1= 1 byte d liu mi c nhn trong khi d liu c vn cn trong thanh ghi SSPBUF. 0= khng c trn. Ch truyn : Khng s dng n bt ny. Bt 5 SSPEN : bt cho php cng ni tip 1= cho php cng ni tip v thit lp SDA v SCL l cc chn ca cng ni tip. 0= khng cho php cng ni tip v thit lp chng nh cc chn vo ra. Bt 4 CKP : SCK : bt iu khin tc ng Ch t : 1= cho xung clock tc ng 0= gi xung clock mc thp ( m bo thi gian thit lp d liu) Ch ch : Khng s dng trong ch ny. Bt 3-0 SSPM3 : SSPM0 : cc bt la chn ch hot ng cng ni tip 1111 : I2C ch t, 10 bt a ch, cho php ngt khi pht hin bt start v bt stop. 1110 : I2C ch t, 7 bt a ch, cho php ngt khi pht hin bt start v bt stop. 1011 : dng phn mm iu khin ch ch (ch t khng dng) 1000 : I2C ch ch, clock = Fosc/(4*(SSPADD+1))


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0111 : I2C ch t , 10 bt a ch. 0110 : I2C ch t, 7 bt a ch. Hnh 10 SSPCON2 : Thanh ghi iu khin MSSP 2(ch I2C)

Bt 7

GCEN : bt cho php gi chung. (duy nht trong ch t ) 1= cho php ngt khi a ch 0000h c nhn vo trong SSPSR. 0= khng cho php gi a ch trn.

Bt 6

ACKSTAT : bt trng thi truyn d liu ) 1= cha nhn c xung 0= nhn c xung t t.

AK C

(duy nht trong ch ch : truyn

AK C

t t

Bt 5

ACKDT : bt d liu 1= khng c xung 0= c xungAK C

AK C

(ch c trong ch ch : nhn d liu )

AK C

Bt 4

ACKEN : bt cho php xung ACK.(ch c trong ch ch: nhn d liu ) 1= khi to xungAK C

trn cc chn SDA v SCL. Bt d liu truyn

ACKDT ). T ng xa bng phn cng. 0= khng cho php xung ACK. Bt 3 RCEN : bt cho php nhn (duy nht trong ch ch ) 1= cho php nhn d liu. 0= khng cho php nhn d liu. Bt 2 PEN : bt cho php iu kin stop. 1= khi to iu kin stop trn cc chn SDA v SCL. T ng xa bng phn cng. 0= khng cho php iu kin stop. Bt 1 RSEN : bt cho php iu kin start (duy nht trong ch ch )


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1= khi to iu kin start trn cc chn SDA v SCL. T ng xa bng phn cng. 0= khng cho php iu kin start. Bt 0 SEN : bt cho php iu kin start hoc cho php kha. Ch ch : 1= khi to iu kin start trn cc chn SDA v SCL. T ng xa bng phn cng. 0= khng cho php iu kin start. Ch t : 1= cho php kha xung clock t ch t truyn v nhn. 0= khng cho php kha xung clock. 2.2.4 Ch ch Ch ch c cho php bi vic ci t hoc xa cc bt SSPM trong thanh ghi SSPCON1 v ci t bt SSPEN. Trong ch ch cc chn SDA v SCL c iu khin bi vi phn cng MSSP. Hot ng ca ch ch c h tr bi vic pht sinh cc ngt khi pht hin bt start v stop. Bt start v stop c xa khi reset hoc khi khi MSSP khng hot ng. Vic iu khin giao tip I2C c th tip tc khi bt stop c t hoc khi bus rng vi c hai bt start v stop u xa. iu khin ch ch bng phn mm ngi s dng ghi m iu khin tt c giao tip bn trong 2 bt start v stop. 1 ch ch c cho php, ngi s dng phi c 6 thao tc: + C iu kin bt start trn chn SDA v SCL. + iu kin lp li bt start trn chn SDA v SCL. + Thanh ghi SSPBUF c khi to truyn d liu hoc a ch. + Thit lp cng giao tip I2C nhn d liu. + Xut hin xungAK C

khi kt thc nhn 1 byte d liu.

+ Xut hin bt stop trn chn SDA v SCL. Cc s kin sau s gy ra ngt MSSP : Bt c v SSPIF c t


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+ Xut hin bt start. + Xut hin bt stop. + Byte d liu chuyn i truyn/nhn. + Truyn xungAK C

.

+Lp li bt start.

Hnh 11 S khi MSSP (I2C ch ch ) 2.2.4.1 Hot ng ca ch ch: I2C ch ng vai tr tch cc trong qu trnh giao tip v iu khin cc I2C t thng qua vic ch ng to ra cc xung giao tip v cc iu kin start, stop khi truyn nhn d liu. Mt byte d liu c th c bt u bng iu kin start, kt thc bng iu kin stop hoc bt u v kt thc vi cng mt iu kin khi ng lp lai (repeated start ). Qu trnh truyn trong ch ch, d liu ni tip c xut ra ti chn SDA trong khi SCL xut ra xung clock ng b ni tip. Byte u tin truyn i s cha a ch ca thit b nhn (7 bt) v 1 bt R/ W . Trong trng hp ny R/ W s c mc logic l 0, d liu 8 bt th truyn 8 bt trong 1 ln, sau mi byte tip theo c


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truyn v 1 bt ni tip.

AK C

c nhn li t t khi t nhn c 1 byte. iu kin

start v stop c xut ra ch ra qu trnh bt u v kt thc ca 1 khung truyn Qu nhn d liu trong ch ch, byte u tin c truyn cha a ch ca thit b t (7 bt ) v 1 bt R/ W . Trong trng hp ny bt R/ W s c gi tr la 1. Vi gi tr ca bt R/ W l 1 th thit b t hiu rng n s nhn d liu. D liu ni tip c nhn ti chn SDA, trong khi u ra xung clock ti chn SCL. 8 bt d liu c nhn trong 1 ln, sau mi byte c nhn th 1 bt truyn ni tip. Tc ngi s dng trong ch I2C tn s ca xung clock l 100 KHZ, 400KHZ hoc 1MHZ 1 qu trnh truyn in hnh nh sau : + S dng iu kin start bng vic ci t bt SEN (SSPCON2 ) cho php Start. + t bt SSPIF, khi MSSP s ch s xut hin ca bt start trc khi c bt k thao tc no xy ra. + Ngi s dng s a a ch ca t vo thanh ghi SSPBUF truyn. + a ch c dch ra ngoi ti chn SDA. + Khi MSSP s nhn btAK C AK C

c truyn, iu

kin start v stop c xut ra ch ra qu trnh bt u v kt thc ca 1 khung

t thit b t v ghi gi tr vo trong thanh ghi

SSPCON2 (SSPCON2). + Khi MSSP s pht sinh 1 ngt xung th 9 bng vic ci t bt SSPIF. + Ngi s dng cp nht 8 bt d liu trong thanh ghi SSPBUF. + D liu c dch ra ngoi ti chn SDA cho n khi 8 bt c truyn xong. + Khi MSSP s nhn btAK C

t thit b t v ghi gi tr vo trong thanh ghi

SSPCON2 (SSPCON2). + Khi MSSP s pht sinh 1 ngt xung th 9 bng vic ci t bt SSPIF. + Ngi s dng to ra 1 iu kin stop bng vic ci t bt PEN (SPCON2) cho php stop.


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+ Ngt c sinh ra t iu kin stop th hon tt 1 khung truyn ni tip. 2.2.4.2 Giao tip I2C ch ch trong qu trnh truyn d liu Qu trnh truyn d liu, xung clock s c a ti chn SCL v d liu c a ti chn SDA. Byte u tin l byte xc nh a ch, 7 bt d liu hoc 1 na ca 10 bt a ch c ghi ti thanh ghi SSPBUF. iu ny s t bt c b m y, b m to xung clock ni tip BRG bt u m v bt u truyn . Mi bt a ch hoc d liu s c dch ra qua chn SDA ti mi sn xung ca xung clock. Sau khi 8 bt c dch ht ra ngoi. I2C ch ngng tc ng ln chn SDA ch tn hiu t I2C t ( tn hiu xung nhn dng cha. Trng thiAK C

) . Ti cnh xung ca xung clock

th 9, I2C ch s ly mu tn hiu t chn SDA kim tra a ch c I2C tAK C

c a vo bt ACKSTAT (SSPCON2).

Cng ti thi im bt BF s t ng c xa, c ngt SSPIF c t v BRG tm ngng hot ng cho ti khi d liu hoc a ch tip theo c a vo thanh ghi SSPBUF, d liu hoc a ch tip tc c truyn i ti cnh xung ca xung clock tip theo. Bt c trng thi BF : Trong qu trnh truyn, bt BF (SSPSTAT) c t khi CPU ghi ti SSPBUF v c xa khi tt c 8 bt c dch ht ra ngoi. Bt c trng thi WCOL : Nu ghi ti thanh ghi SSPBUF khi ang truyn th bt WCOL c t v ni dung b m khng thay i. Bt WCOL phi c xa bng phn mm. Bt c trng thi ACKSTAT : Trong qu trnh truyn, bt ACKSTAT (SSPCON2) c xa khi thit b tK gi mt xung AC ( AK C

=0) v c t khi thit b t khng gi xungAK C

AK C

(

AK C

=1). Thit b t gi 1 xung

khi nhn ng a ch ca n hoc khi nhn

d liu.


Khoa in t

Hnh 12 Gin xung I2C ch ch trong qu trnh truyn d liu (7 hoc 10 bt a ch)

2.2.4.3 Giao tip I2C ch ch trong qu trnh nhn d liu


Khoa in t

Qu trnh nhn d liu trong ch ch c cho php bng cch t bt cho php nhn RCEN (SSPCON2). Cn ch l khi MSSP phi trng thi ngh trc khi bt RCEN c t hoc bt RCEN s c b qua. BRG bt u m, d liu s c dch vo trong I2C ch ti mi cnh xung ca chn SCL. Sau sn xung ca xung clock th 8, c cho php nhn t ng c xa, gi tr trong thanh ghi SSPSR c cp nht vo trong thanh ghi SSPBUF, bt c BF v bt c SSPIF c t v BRG ngng m, chn SCL c a xung mc thp. Khi MSSP trng thi ngh v ch lnh tip theo. Khi b m sn sng, bt c BF s t ng c xa, lc ny ta c th gi 1 xung ci t bt cho php ACKEN(SSPCON2). Bt c trng thi BF : Trong qu trnh truyn, bt BF c t khi 1 byte a ch hoc d liu c a vo trong thanh ghi SSPBUF t SSPSR. N c xa khi thanh ghi SSPBUF c c. Bt c trng thi SSPOV : Trong qu trnh truyn, b SSPBUF c t khi 8 bt c nhn vo trong thanh ghi SSPSR v bt c BF c t t qu trnh nhn trc. Bt c trng thi WCOL : Nu ta ghi ti thanh ghi SSPBUF khi nhn ang hot ng th bt c WCOL c t v ni dung b m khng thay i.AK C

bng cch


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Hnh 13 Gin xung I2C ch ch trong qu trnh truyn d liu (7 bt a ch ) 2.2.4.4 I2C Ch ch tnh ton iu kin start


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Khi to iu kin start, ngi s dng t bt SEN(SSPCON2) cho php start. Nu chn SDA v SCL ly mu mc cao, tc baud c cp nht lai v cha trong thanh ghi SSPADD v bt u m. Nu hai chn SDA v SCL ly mu mc cao v thi gian ra ca tc baud (Tbrg ), chn SDA xung mc thp. Ti thi im SDA a xung mc thp trong khi SCL vn mc cao th iu kin start hnh thnh v bt S (SSPSTAT) c t. Trong trng hp SCL v SDA trng thi logic thp hoc trong qu trnh iu kin start, chn SCL c a v trng thi logic thp trc khi chn SDA c a v trng thi logic thp th iu kin start khng c hnh thnh, c ngt BCLIF s c t v I2C s trng thi ngh (IDLE).

Hnh 14 Qu trnh to bt start 2.2.4.5 Lp li iu kin start to iu kin start lp li trong qu trnh truyn d liu, trc ht cn t bt RSEN(SSPCON2). Sau khi t bt RSEN, chn SCL c a xung mc logic thp, chn SDA c a ln mc logic cao, BRG ly gi tr t thanh ghi SSPADD vo bt u qu trnh m. Sau khong thi gian TBRG chn SCL cng c a ln mc logic cao trong khong thi gian TBRG tip theo. Trong khong


Khoa in t

thi gian TBRG k tip , chn SDA li c a xung mc thp trong khi SCL vn c gi mc logic cao. Tai thi im bt S (SSPSTAT) c t bo hiu iu kin start c hnh thnh, bt RSEN t ng c xa v c ngt SSPIF s c t sau 1 khong thi gian TBRG na. Lc ny a ch ca I2C t c th c a vo thanh ghi SSPBUF, sau ch vic a tip a ch hoc d liu tip theo vo thanh ghi SSPBUF mi khi nhn c tn hiuAK C

t I2C t, I2C ch

s t ng to tn hiu lp li start cho qu trnh truyn d liu lin tc.

Hnh 15 Gin xung trong qu trnh to iu kin lp li bt start 2.2.5 Ch t Trong ch t cc chn SCL v SDA phi c thit lp l u vo. Khi MSSP s p trng thi u vo thnh trng thi d liu ra khi cn thit (thit b t truyn ). Ch t lun tn ti 1 ngt trn 1 a ch ph hp. La chn cc bt c th chn ngt bt start v stop. I2C ca vi iu khin s c iu khin bi mt vi iu khin hoc mt thit b ngoi vi khc thng qua cc a ch. Khi a ch ny ch n vi iu khin , th ti thi im ny v ti thi im d liu truyn nhn xong sau vi iu khin s to ra xungAK C

bo hiu kt thc d liu. Gi tr trong


Khoa in t

thanh ghi SSPSR s c a vo thanh ghi SSPBUF. Tuy nhin xung khng c to ra nu mt trong cc trng hp sau :

AK C

s

+ Bt BF (SSPSTAT ) bo hiu b m y, c t trc khi qu trnh truyn nhn xy ra. + Bt SSPOV(SSPCON2) c t trc khi qu trnh truyn nhn xy ra Trong cc trng hp trn thanh ghi SSPSR s khng a gi tr vo trong thanh ghi SSPBUF, nhng bt SSPIF (PIR1) c t. qu trnh truyn nhn d liu c tip tc , cn c d liu t thanh ghi SSPBUF vo trc, khi bt BF s t ng c xa , cn bt SSPOV phi xa bng phn mm. 2.2.5.1 nh a ch Khi khi MSSP c cho php, n s ch s xut hin ca bt start. Theo sau bt start l 8 bt c dch vo trong thanh ghi SSPSR. Cc bt a vo s c ly mu ti cnh ln ca xung clock. G tr ca thanh ghi SSPSR c so snh vi gi tr ca thanh ghi SSPADD ti canh xung ca xung clock th 8. Nu kt qu so snh bng nhau, tc l I2C ch ch nh i tng giao tip l vi iu khin ang ch t. Bt BF v SSPOV s c xa v 0 v gy ra cc s kin sau : + Gi tr thanh ghi SSPSR c cp nht vo trong thanh ghi SSPBUF. + B m y, c BF c t. + Mt xungAK C

c to ra.

+ C ngt SSPIF c t (PIR1) ( ngt c to ra nu cho php ) ti cnh xung ca xung clock th 9. Trong ch a ch 10 bt, 2 byte a ch cn c nhn vo bi thit b t khi bt R/ W = 0 so snh. Byte u tin c nh dng 11110A9A80 trong A9,A8 l hai bt MSB ca 10 bt a ch. Byte th hai l 8 bt a ch cn li. Qu trnh nhn dng a ch ca MSSP ch I2C, ch t 10 bt a ch nh sau : 1 : Byte u tin cha 2 bt MSB ca 10 bt a ch c nhn trc, bt SSPIF,BF v UA (SSPSTAT) c t.


Khoa in t

2 : Byte th hai cha 8 bt a ch thp c cp nht vo thanh ghi SSPBUF, bt UA b xa. 3 : c thanh ghi SSPBUF (bt BF b xa ), xa c ngt SSPIF. 4 : Nhn 8 bt a ch thp ca byte th 2 , cc bt SSPIF,BF v UA c t . 5 : Cp nht vo thanh ghi SSPADD cc bt byte u tin. Nu a ch l ng xung clock chn SCL c khi to v bt UA c t. 6 : c thanh ghi SSPBUF (xa bt BF) v bt c SSPIF b xa. 7 : Nhn tn hiu start. 8 : Nhn byte a ch cao , bt SSPIF v BF c t. 9 : c thanh ghi SSPBUF(xa bt BF) v xa c ngt SSPIF. 2.2.5.2 Giao tip I2C ch t trong qu trnh nhn d liu Trong qu trnh nhn d liu ch t, cc bt a ch s c a vo trc. khi bt R/ W ca byte a ch c gi tr bng 0 v a ch l ng. Bt R/ W ca thanh ghi SSPSTAT c xa v 0. a ch nhn c a vo trong thanh ghi SSPBUF v ng d liu SDA c a v mc logic thp (xungAK C

). Khi

iu kin trn byte a ch tn ti thi xung NOT ACK c sinh ra. iu kin trn xy ra th 2 bt BF(SSPSTAT) c t, hoc bt SSPOV(SSPCON1) c t. Ngt MSSP khi truyn mi byte d liu, bt c SSPIF(PIR1) c t, phi c xa bng phn mm. Thanh ghi SSPSTAT c s dng xc nh trng thi ca byte. Khi bt SEN (SSPCON2) c t, sau khi 1 byte d liu c nhn, xung clock t chn RC3/SCK/SCL s c a xung mc thp. Mun khi to li xung clock ta t bt CKP(SSPCON)


Khoa in t

Hnh 16 Gin xung ca I2C ch t 7 bt a ch trong qu trnh nhn d Liu (bt SEN = 0 )


Khoa in t

Hnh 17 Gin xung ca I2C ch t 10 bt a ch trong qu trnh nhn d liu (bt SEN = 0 )


Khoa in t

Hnh 18 Gin xung ca I2C ch t 7 bt a ch trong qu trnh nhn d liu (bt SEN = 1 )


Khoa in t

Hnh 19 Gin xung ca I2C ch t 10 bt a ch trong qu trnh nhn d liu (bt SEN = 1 ) 2.2.5.3 Giao tip I2C ch t trong qu trnh truyn d liu


Khoa in t

Khi bt R/ W ca byte a ch c t v a ch c ch nh l ng. Bt R/ W ca thanh ghi SSPSTAT c t. a ch c nhn v c a vo trong thanh ghi SSPBUF. 1 xungAK C

s c to ra v gi trong bt th 9, xung clock

chn RC3/SCK/SCL c ko xung mc thp bt chp trng thi ca bt SEN. Khi I2C ch s khng c a xung clock vo I2C t cho n khi qu trnh truyn d liu trng thi sn sng. Qu trnh truyn d liu phi c a vo trong thanh ghi SSPBUF v ng thi a vo trong thanh ghi SSPSR. Tip theo cho php xung chn RC3/SCK/SCL bng cch t bt CKP (SSPCON). 8 bt trong byte d liu s c dch dn ra ti mi sn xung ca xung clock. Nh vy d liu s sn sng ng ra khi xung clock mc logic cao, gip cho I2C ch nhn c ti mi cnh ln ca xung clock. Ti sn ln ca xung clock th 9, d liu c dch ht vo I2C ch, xungAK C

s c to ra I2C ch. Nu chn SDA c d mc cao v d liu c cht bi I2C t , thanh ghi SSPSTAT s c reset. I2C t s ch tn

K truyn hon thnh th xung NOT AC s c to ra. Trong trng hp xung

AK C

hiu ca bt start tip tc truyn byte d liu tip theo, a byte d liu vo thanh ghi SSPBUF v t bt CKP. Ngt MSSP xy ra khi kt thc truyn 1 byte d liu. bt SSPIF c t ti sn xung ca xung clock th 9 v phi xa bng phn mm, m bo s c t khi byte d liu tip theo truyn xong.


Khoa in t

Hnh 20 Gin xung ca I2C ch t 7 bt a ch trong qu trnh truyn d liu


Khoa in t

Hnh 21 Gin xung ca I2C ch t 10 bt a ch trong qu trnh truyn d liu


Khoa in t

2.2.6 Tc baud Trong ch ch ca giao tip I2C, xung giao tip ni tip c to ra t RRG (bau rate generator), gi tr xc nh tn s xung clock ni tip c ly t 7 bt thp ca thanh ghi SSPADD. Khi d liu c a vo thanh ghi SSPBUF, bt BF c t v BRG t ng m ngc v 0 v dng li, chn SCL c gi nguyn trng thi trc . Khi d liu tip theo c a vo, BRG s cn mt khong thi gian t ng reset li gi tr tip tc qu trnh m ngc. Mi vng lnh (c thi gian )Tcy BRG s gim gi tr 2 ln. Trong ch ch, thanh ghi SSPADD s khng c s dng cha a ch, thay vo chc nng ca SSPADD lc ny l thanh ghi cha gi tr ca BRG.

Hnh 22 S khi BRG (baud rate generator )

Cc gi tr c th ca tn s xung ni tip do BRG to ra c lit k trong bng sau :


Khoa in t

2.2.6.1 Gim st xung clock Gim st xung clock xut hin khi ch trong thi gian truyn, nhn hoc iu kin lp li start/stop. Khi chn SCL mc cao th th tc baud c dng li t b m cho n khi chn SCL c ly mu mc cao. Khi chn SCL c ly mu mc cao, tc baud c cp nht li cha trong SSPADD v bt u m.

Hnh 23 Tc baud vi vic gim st xung clock

2.2.7 a ch gi chung Qu trnh truyn nhn trong giao tip I2C , cc bt a ch c truyn u tin trong byte th nht sau bt start nhm xc nh a ch ca thit b t cn giao


Khoa in t

tip. Bn cnh I2C cung cp mt a ch m c th gi tt c cc thit b I2C t. a ch ny l mt trong 8 a ch c bit ca protocol I2C. a ch ny c nh dng l 1 chui cc bt 0 vi bt R W = 0. Vic gi a ch ny c cho php bng cch t bt GCEN(SSPCON2). Sau khi xc nh bt start, 8 bt tip theo c dch vo trong thanh ghi SSPSR v a ch ny c so snh vi SSPADD. Nu a ch gi chung l ng, SSPADD s truyn ti SSPBUF 8 bt v c BF c t v trn sn xung ca bt th 9 ( btAK C

) bt c ngt SSPIF c t.

Trong ch 10 bt, SSPADD i hi phi cp nht na th 2 ca a ch ng v bt UA (SSPSTAT ) c t. Nu a ch gi chung c ly mu khi bt GCEN t. Trong khi thit b t thit lp ch 10 bt a ch th na th 2 ca a ch cha cn thit, bt UA s khng c t v thit b t s bt u nhn d liu sau btAK C

.

Hnh 24 a ch gi chung trong ch t ( ch 7 hoc 10 bt a ch )

2.2.8 Tnh ton thi gian chui Mt chui liuAK C

AK C

c cho php bng cch t bt cho php ACKEN th

(SSPCON2). Khi bt ny c t, chn SCL c ko xung mc thp v dAK C

c xut ra trn chn SDA. Nu mun khi ng mt xung

AK C


Khoa in t

bt ACKDT c xa. Nu khng ta t bt ACKDT trc khi bt u chui

AK C

. Khi chn SCL ly mu mc cao, BRG m ti TBRG , chn SCL c ko xung thp. Theo sau n l bt ACKEN s t ng c xa. BRG khng hot ng v khi MSSP ch ngh. Bt c trng thi WCOL : Nu ta ghi vo thanh ghi SSPBUF khi mt chuiAK C

ang hoat ng th

bt c WCOL c t v ni dng b m khng thay i.

Hnh 25 Gin xung chui ACK 2.2.9 Tnh ton iu kin stop Tn hiu stop c a ti chn SDA khi kt thc d liu truyn hoc nhn bng cch t bt PEN (SSPCON2) . Kt thc qua trnh truyn hoc nhn, chn SCL c ko xung mc thp sau sn xung th 9 ca xung clock. Khi bt PEN c t, I2C ch s ko SDA xung mc thp. Khi SDA c ly mu mc thp, BRG c cp nht li v bt u m ngc v 0. Sau 1 khoang thi gian T BRG , chn SCL c a ln mc logic cao v sau 1 khong thi gian TBRG na chn SDA cng c a ln mc cao. Ngay ti thi im bt P(SSPSTAT) c t ( iu kin stop c to ra ). Sau 1 khong thi gian TBRG na bt PEN t ng c xa v c ngt SSPIF c t.


Khoa in t

Hnh 26 Gin xung trong qu trnh to iu kin lp li bt stop 2.2.10 Ch a ch Trong ch a ch, ngt c sinh ra khi xut hin iu kin start v stop hoc khi bus rng. Bt start v stop c xa khi reset hoc khi MSSP khng s dng. iu khin giao tip I2C c th ly khi bt P (SSPSTAT) c t hoc khi bus trng thi ngh vi c hai bt start v stop b xa. Khi bus bn, MSSP s cho php ngt khi xut hin iu kin stop. Trong hot ng ch a ch, chn SDA cn c kim tra, nu mc tn hiu ch u ra. Vic kim tra ny c thc hin bi phn cng vi kt qu c t trong bt BCLIF. Cc trng thi c th b mt gim st l : + Chuyn i a ch. + Chuyn i d liu. + 1 iu kin start. + 1 iu kin lp li start. + 1 iu kin2.2.10.1AK C

.

Truyn thng a ch, xung t bus v gim st bus


Khoa in t

Truyn thng a ch c h tr gim st bus. Khi u ra ch l cc bt a ch hoc d liu trn chn SDA. Gim st ch xy ra khi u ra ch l 1 trn chn SDA v d liu ly mu trn chn SDA l 0 th xung t bus c xy ra. Ch s t bt c ngt xung t bus v BCLIF v reset cng I2C n v trng thi ngh. Nu truyn ang hot ng, khi va chm bus xut hin, truyn s dng li, c BF c xa, cc chn SDA v SCL s dng hot ng v c th ghi ti thanh ghi SSPBUF. Khi s dng dch v ngt xung t bus v nu bus I2C rng, ngi s dng c th tip tc truyn thng bng cch khi to mt iu kin start. Nu 1 start, lp li start, stop hoc iu kinAK C

ang hot ng khi xut hin

xung t bus, iu kin ny s khng c tc dng, cc chn SDA v SCL s dng v bt iu khin tng ng trong thanh ghi SSPCON2 c xa. Khi s dng dch v ngt do xung t bus v khi bus I2C rng ngi s dng c th tip tc truyn thng bng cch khi to iu kin start. Thit b ch s tip tc gim st cc chn SDA v SCL. Nu iu kin stop xut hin, bt SSPIF s c t. Qu trnh ghi ti thanh ghi SSPBUF s bt u truyn d liu bt d liu u tin.

Hnh 27 Gin xung giao tip I2C ch a ch khi c xung t bus, xung 2.2.10.2 Xung t bus trong khi c iu kin start Trong khi c iu kin start, xut hin xung t bus th :AK C


Khoa in t

+ SDA v SCL c ly mu mc thp vo thi im bt u iu kin start. + SCL c ly mu mc thp trc khi SDA ko xung mc thp. Trong khi c 1 iu kin start c hai chn SDA v SCL u c theo di. Nu chn SDA mc thp hoc SCL mc thp th s xut hin : + iu kin start khng c tc dng. + bt c BCLIF c t + Khi MSSP ret n trng thi ngh. Khi chn SDA ly mu mc cao, BRG cp nht t SSPADD v m li v 0. Nu chn SCL ly mu mc thp trong khi SDA mc cao, 1 s xung t bus xut hin. Nu chn SDA ly mu mc thp trong thi gian m ny, BRG s reset. Tuy nhin nu ly mu trn SDA l 1, chn SDA mc thp thi im cui ca b m. BRG s c cp nht li v m li v 0. Nu chn SCL ly mu bng 0 trong thi gian ny th khng c s xung t bus, thi im cui ca b m BRG, chn SCL xung thp.


Khoa in t

Hnh 28 Xung t bus trong thi gian iu kin start( duy nht chn SDA)

Hnh 29 Xung t bus trong thi gian iu kin start( SCL=0)

Hnh 30 BRG ret gim st SDA trong thi gian iu kin start


Khoa in t

2.2.10.3 Xung t bus trong thi gian lp li iu kin start Trong thi gian lp li iu kin start, xut hin 1 s xung t bus nu: + Trn chn SDA c ly mu mc thp khi SCL t thp ln cao. + SCL xung mc thp trc khi SDA thp. Khi SDA ln mc cao BRG cp nht li vi thanh ghi SSPADD v b m s m ngc v 0. Chn SCL ly mu mc cao chn d liu SDA. Nu SDA mc thp khi 1 s xung t bus xut hin ( trng hp 1 ) Nu SDA c ly mu mc cao, BRG s cp nht li v bt u m, nu SDA t mc cao xung thp trc khi BRG m xong th khng xut hin xung t bus. Nu SCL t cao xung thp trc khi BRG m xong v SDA khng xc nh mc th xut hin xung t bus. ( trng hp 2 ) Nu kt thc BRG m c hai SCL v SDA u mc cao. Chn SDA c iu khin xung thp v BRG s c cp nht li v bt u m. Khi kt thc m, bt chp trng thi ca chn SCL, chn SCL c a xung thp v iu kin lp li start hon thnh.

Hnh 31


Khoa in t

Xung t bus trong thi gian lp li iu kin start ( trng hp 1)

Hnh 32 Xung t bus trong thi gian lp li iu kin start ( trng hp 2) 2.2.10.4 Xung t bus trong thi gian iu kin stop Xung t bus trong thi gian iu kin stop nu : + Sau khi chn SDA ln cao, SDA c ly mu mc thp sau BRG m ht. + SCL c ly mu mc thp trc khi SDA ln cao. iu kin stop bt u khi chn SDA mc thp, SDA c ly mu thp. SCL ln cao. BRG c cp nht li v bt u m ngc v 0. Sau khi BRG m xong , SDA c ly mu, nu chn SDA c ly mu thp th xut hin xung t bus ( trng hp 1) . Nu SCL c ly mu thp trc khi SDA cho php ln cao th cng xut hin xung t bus. ( trng hp 2)


Khoa in t

Hnh 33 Xung t bus trong thi gian iu kin stop ( trng hp 1)

Hnh 34 Xung t bus trong thi gian iu kin stop ( trng hp 2) 2.2.11 v d : c v ghi gi tr vo ds1307 hin th lcd : Code :#include #include #include #include #pragma config OSC = HS #pragma config IESO = OFF


Khoa in t

#pragma config PWRT = OFF #pragma config WDT = OFF #pragma config WDTPS = 32768 #pragma config MCLRE = ON #pragma config LVP = OFF #pragma config DEBUG = OFF #pragma config CP0 = OFF #pragma config CP1 = OFF #pragma config CPB = OFF #pragma config CPD = OFF #pragma config WRT0 = OFF #pragma config WRT1 = OFF #pragma config WRTB = OFF #pragma config WRTC = OFF #pragma config WRTD = OFF #pragma config EBTR0 = OFF #pragma config EBTR1 = OFF #pragma config EBTRB = OFF #define rs PORTCbits.RC1 #define en PORTCbits.RC2 #define gio PORTBbits.RB0 #define phut PORTBbits.RB1 #define set PORTBbits.RB2 #define LOA PORTAbits.RA0 void delay(unsigned int t); void loa(void); void ghilenh(unsigned char a); void ghidulieu(unsigned char b); void chuoi(char *s); void dieukhien(void); void ghi_ds(unsigned char diachighi, unsigned char dulieu); void doc_ds(unsigned char diachidoc); int bcd_int(char x); int int_bcd(int y); void chedo(void); void hienthi(void); char M[32]; int s;

Trng i Hc Cng Nghip H Niint gio=0,phut=0,giay=0; int dem=0,dem1=0;

Khoa in t

void delay(unsigned int t) { unsigned int i; for(i=0;i4)*10)+(x&0x0F)); } //********************************* int int_bcd(int y) { return((((y/10)

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