CmosRazavi 22/9/068.3 8.78.4 8.88.5 8.98.6 8.108.7 8.118.8
8.18.9 8.28.10 8.38.11 8.48.13 8.13 problem 8.5 problem 8.9
CHAPTER 13
NEW PREVIEW----- ---------
3.17 3.17 Eq. (3.123) Eq. (3.119)
CHAPTER 14 - New Chapter, Oscillators
CHAPTER 15 - New Chapter, Phase-Locked Loops
CHAPTER 16 - Was Chapter 14 in Preview Ed.
Change all chapter references in solutions manual from 14 to
16.
CHAPTER 17 - Was Chapter 15 in Preview Ed.
Change all chapter references in solutions manual from 15 to
17.
CHAPTER 18 - Was Chapter 16 in Preview Ed.
NEW PREVIEW----- ---------
18.3 16.3 Fig. 18.12(c) Fig. 16.13(c)18.8 16.8 Fig.
18.33(a,b,c,d) Fig. 16.34(a,b,c,d)
Also, change all chapter references from 16 to 18.SIC 5328
Design of Analog CMOS Integrated Circuits
Behzad Razavi
Errata in Problem Sets
Chapter 2 In Eq. (2.44),
n
must be in the numerator.Chapter 3 Call the third problem 3.2.
In Problem 3.2, Fig. 3.68(d), change the gate voltage ofM2to V
b2. In Problem 3.4, Fig. 3.71(a), change the gate voltage
ofM
=
1 to Vb1.
In Fig. 3.72(e), Vb1 must be changed to Vin.
In Fig. 3.73(h), the output is at the source of M2. In Problem
3.10(c), the question must be phrased as: Whichdevice enters the
triode region first as V
out
falls? In Problem 3.13, first sentence should read: ... withW=L
=50=0:5 ... In Problem 3.16(a), do not neglect channel-length
modula-tion in the triode region.Chapter 4 In Problem 4.2, assume
I
SS
= 1 mA and change part (a) to:Determine the voltage gain. In
Problem 4.6, assume = 0. In Problem 4.9, assume = = 0. In Problem
4.11, assume I
D5 = 20 A. In Problem 4.13, change the figure number to
4.8(a).Chapter 5 In Problem 5.16(d), assume V
TH
does not vary with tem-perature.Chapter 6 In Problem 6.4(b) and
(d), assume 6= 0.Chapter 7 The second sentence of Problem 7.2
should read: Assume(W=L)1 = 50=0:5; ID1 = ID2 = 0:1 mA ...
In Problem 7.20, change ID1 and ID2 to 0.05 mA.
In Problem 7.24, change the bias current to 0.1 mA.Chapter 8 In
Problem 8.10, change the tolerable gain error to 5%. In Problem
8.15, Fig. 8.55(b), call label the top G
m
blockG
m2. The output is at the output nodes of Gm2.Chapter 10 In
Problem 10.11, change I
SS
to 0.25 mA and (W=L)5;6 to60/0.5. In Problem 10.12, add:
Maximize V
GS14 = VGS15 whileleaving at least 0.5 V across I1. Also, in
part (b), change M2to M1. Problem 10.17 should read: ... between
the gate and thedrain of M2 or M3. In Fig. 10.42, change the gate
voltage of M3;4 to Vb1. In Problem 10.19(c), change A0 in the
numerator to A.Chapter 11 In Problem 11.13, ... such that the
circuit operates withV
DD
= 3 V. In Problems 11.17 and 11.18, the top terminal of R2
shouldbe connected to the top terminal of R1. In Problem 11.22,
assume K = 4.Chapter 12 In Problem 12.8, assume C
H
= 1 pF. In Problem 12.12, assume all switches are NMOS devices.
In Problem 12.14, assume C
in
= 0:2 pF and calculate C1and C2. In Problem 12.16, the output is
sensed at the drains of M1and M2.Chapter 13 In Problem 13.5, change
the figure number to 13.6(a).
CmosRazavi 22/9/06
SIC 328328
Chapter2 MOS2.12.22.32.42.52.5 a2.5 b2.5 c2.5 d2.5 e
2.62.6 a2.6 b2.6 c2.6 d2.6 e
2.72.7 a2.7 b2.7 c2.7 d
2.82.8 a2.8 b2.8 c
2.92.9 a2.9 b2.9 c2.9 d2.9 e
2.102.10 a2.10 b2.10 c
2.112.11 a2.11 b2.11 c2.11 d
2.122.12 a2.12 b2.12 c2.12 d
2.132.142.152.162.172.182.192.202.212.222.232.242.252.262.26
a2.26 b
2.272.28
Chapter3 3.8 3.13.9 3.23.11 3.33.12 3.43.13 3.53.14 3.63.15
3.73.16 3.83.17 3.93.18 3.103.19 3.113.20 3.123.21.223.13.143.1
3.153.2 3.163.3 3.183.4 3.193.5 3.203.6 3.213.7 3.223.10 3.233.23
3.243.24 3.253.25 3.263.26 3.273.27 3.283.28 3.29
Chapter4 4.12 4.14.14 4.34.15 4.44.16 4.54.17 4.64.18 4.74.13
4.2
4.19 4.84.20 4.94.21 4.104.22 4.114.23 4.124.24 4.134.1 4.144.2
4.154.3 4.164.4 4.174.5 4.184.6 4.194.7 4.204.8 4.214.9 4.224.10
4.234.11 4.244.254.26
Chapter5 5.16 5.15.17 5.25.18 5.35.19 5.45.20 5.55.21 5.65.22
5.75.23 5.85.1 5.95.1 a5.1 b5.1 c5.1 d e
5.2 5.105.3 5.115.3 a5.3 b5.3 c
5.4 5.125.4 a5.4 b
5.5 5.135.5 a5.5 b5.5 c
5.6 5.145.6 a5.6 b
5.7 5.155.7 a5.7 b
5.8 5.165.9 5.175.10 5.185.11 5.195.12 5.205.13 5.215.14
5.225.15 5.23
Chapter6 6.7 6.16.8 6.26.9 6.36.10 6.46.11 6.56.1 6.66.2 6.76.3
6.86.3 a6.3 b6.3 c6.3 d6.3 e6.3 f
6.4 6.96.4 (a.b)6.4 c6.4 d
6.5 6.106.5 a6.5 b
6.6 6.116.126.136.146.156.166.176.17 a6.17 b
Chapter7 7.17.27.37.(4.5)7.67.6 (a.b)7.6(c.d.e)7.6(e.f)
7.77.7(a.b.c)7.7(d)
7.87.97.10.117.127.137.147.157.167.177.18.197.207.217.227.237.247.257.26
Chapter8 8.5 8.18.6.7.8 8.2.3.48.9 8.58.10 8.68.11 8.78.1 8.88.2
8.98.3 8.108.4
8.118.128.138.12.13add8.148.158.168.178.188.198.208.218.228.23
Chapter9 9.19.1 a9.1 b9.1 c
9.29.2 (a.b)9.2 c9.2 d
9.39.49.59.69.79.89.99.109.119.129.139.149.159.169.179.189.199.209.219.229.239.249.25
Chapter10
10.110.210.310.410.510.610.710.810.910.1010.1110.1210.1310.1410.1510.1610.1710.1810.1910.19
d add10.19 d10.19 (a.b.c)
10.20
Chapter11
11.111.211.311.411.511.611.7.811.911.10.1111.1211.1311.12.13add11.1411.1511.1611.1711.18.1911.2011.2111.22
Chapter12 12.112.212.312.412.512.612.712.8.9
12.1012.12.13.1412.1512.16.1712.18.1912.20.2112.22
Chapter13
13.113.213.313.4.513.613.7.8.913.1013.1113.1213.13.14.1513.1613.17.18
13.1913.20
Chapter14 A
14.114.2.3.414.4.514.5.6.714.8.914.1014.1114.1214.13
Chapter14 14.114.(2.3)
14.414.514.6.714.4.5.6add14.714.814.914.1014.1114.12.1314.1414.15.16
Chapter15 15.115.2.315.415.5.615.715.815.9.1015.1115.12
Chapter15 A
15.1.215.3.415.5.6.715.8.915.10.11.1215.1315.1415.1515.16
Chapter16 to 18 16.116.216.316.416.516.616.716.8.9
16.1016.1116.12.1316.1416.1516.1616.17
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