Solution for Analog and Digital Circuits - · PDF fileSolution for Analog and Digital Circuits ... design a 8 bit Comparator using IC 7485 ... Draw the circuit of JK –FF using NAND

Mumbai University I.T (Semester -III)

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Solution for Analog and Digital Circuits

December 2015

Index

Q.1)

a) …………………………………………………………………………. 2-3

b) ………………………………………………………………………….3

c) …………………………………………………………………………. 4

d) …………………………………………………………………………. 4-6

e) …………………………………………………………………………. 6-8

f) …………………………………………………………………………. 9

Q.2)

a) …………………………………………………………………………. 10-11

b) …………………………………………………………………………. 11-12

c) ………………………………………………………………………….. 13-15

Q.3)

a) …………………………………………………………………………. 16-17

b) …………………………………………………………………………. N.A

c) …………………………………………………………………………. N.A

Q.4)

a) …………………………………………………………………………. 18-19

b) …………………………………………………………………………. N.A

c) …………………………………………………………………………. 19-23

Q.5)

a) …………………………………………………………………………. 23-25

b) …………………………………………………………………………. N.A

Q.6)

a) …………………………………………………………………………. 27

b) ………………………………………………………………………….28

c) ………………………………………………………………………….28-30

d) …………………………………………………………………………30



Q1) Solve any five

a) Convert

(i) (174.03125)10 in octal number and (DB.94)16 in binary

Ans:

Number Quotient Remainder

174/ 8 21 6

21/8 2 5

2/8 0 2 ↑

Number

0.3125 X 8 = 2.5000 2

0.5000 X 8 = 4.0000 4

0.0000 X 8 =00000 0

Ans: (174.03125)10 = (256.240)8

(ii) Make subtraction using 2’s complement method (52)10 –

(65)10



Ans:

b) Compare schottky barrier diode and PN junction diode.

Ans:



c) Derive the relation between alpha and beta.

ANS:

d) List the ideal characteristics is OPAMP

ANS: The ideal characteristics of OPAMP are as follows:

1)Input resistance Ri is infinite.

2) Output resistance Ro is zero.

3) Voltage gain Av is infinite.

4) Bandwidth B.W. is infinite.

5) CMRR is infinite



6) Slew rate S is infinite

7) Input offset voltage Vios is zero.

8) PSRR is zero

9)Input bias current IB is zero

10) Input offset current IIOS is zero



e) Prove that NAND gate is universal

Ans : The conversion of each logic function into an expression using only NAND

gates is given below .As any logic function can be converted using NAND gate it is stated as universal gate.







f) Convert T-FF TO D-FF

ANS:



Q 2)

(a) Draw block diagram of shunt regulator and explain its working

ANS:

OPERATION: 1) From fig above it is clear that the output voltage is given by:

VO = VZ + VBE.

2) VIN I is the unregulated dc power supply sending a current II through the limiting resistor R.

3) Regulation action:

* If the output voltage decreases due to any reason, then (VZ + VBE) will also decrease .But VZ is constant so VBE will decrease.

*This will reduce the collector IC . So more current will flow through the load and the load voltage will increase.

* If the output voltage increases, then exactly opposite action will take place to regulate the output voltage.

Advantages:

*It is possible to provide temperature compensation without any additional circuitry.

*Better regulation R0 is of low value. This is an important advantage.



*Better regulation as compared to the simple Zener regulator.

Disadvantage

*The power dissipation taking place in the series resister R ,Zener diode and transistor

Application:

*These regulators are used in low power, less expensive application.

(b) Derive the expression for the stability factor ‘S’ of a voltage divider bias circuit

Ans:





(c) Draw the circuit diagram of differentiate using OPAMP and explain

Ans:





Input and Output Voltage Waveform



Q3 )

a)] Explain the summing amplifier using OPAMP .Derive the expression for output voltage.

Ans : It is possible to apply more than one input signal to an inverting amplifier .This circuit will then add all these input signals to produce their addition at the output.

*Such a circuit will then be called as an adder or a summing amplifier.

* Depending on the polarity or sign at the output voltage the adder circuits can be classified into two categories as:

1) Inverting adder 2) Non-inverting adder

Inverting adder or inverting summing amplifier

* The fig. shows the 'inverting summing amplifier' configuration with three input V1, V2 and V3.

*Depending on the relation between the feedback resistor Rf and the three input resistance R1,R2,R3 the same circuit shown in the fig. can be used as either a summing amplifier , scaling amplifier or averaging amplifier.

* V1,V2,V3 are the three input signals applied simultaneously to the inverting terminal os the OP-AMP through resistors R1,R2,R3 respectively.

* V1,V2 and V3 are measured with respect to ground Rf is the feedback resistor.



*So the configuration of the fig. is basically an inverting amplifier with three inputs.

*Let the currents through the resistors R1,R2,R3 be I1,I2and I3.

*For the analysis of this circuit we assume that the OP-AMP is ideal. Hence its input resistance is Ri = infinite.Therfore the currents IB1 AND IB2 are zero. In addition to this , Node A is at virtual ground.

Expression for the output voltage:

Apply KCL at node A I1 + I2 + I3 = IB2 + IF



(b)

simplify this equation and realize using basic gates .

Ans: N.A

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(c) Minimize the following expression using K-map

Y- Ʃ m (1,2,9,10 ,11,14,15) .Implement the circuit using minimum number of gates.

Ans: N.A

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Q4)

(a) design a 8 bit Comparator using IC 7485

Ans: 8-Bit Comparator

An 8-bit comparator compares the two 8-bit numbers by cascading of two 4-bit

comparators. The circuit connection of this comparator is shown below in which

the lower order comparator A<B, A=B and A>B outputs are connected to the

respective cascade inputs of the higher order comparator.

For the lower order comparator, the A=B cascade input must be connected High,

while the other two cascading inputs A ,B must be connected to LOW. The outputs

of the higher order comparator become the outputs of this eight-bit comparator.

http://www.electronicshub.org/wp-content/uploads/2015/07/7485-2.jpg



Applications of Comparators

These are used in the address decoding circuitry in computers and microprocessor

based devices to select a specific input/output device for the storage of data.

These are used in control applications in which the binary numbers representing

physical variables such as temperature, position, etc. are compared with a reference

value. Then the outputs from the comparator are used to drive the actuators so as to

make the physical variables closest to the set or reference value.

Process controllers

Servo-motor control

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(b) Implement the following functions using 8:1 Mux .

F(A,B,C,D ) = Ʃ m(0,1,2,4,6,9,12,14)

Ans: N.A

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C) What is shift register? Mention different modes of operation of shift register.

Ans: The binary data in a register can be moved within the register from one flip flop to the other or outside it with the application of clock pulse.

*The registers that allow such data transfers are called as shift registers.

* Shift registers are used for data storage, data transfer and certain arithmetic and logic operations.

Modes of operations of a shift registers

The various modes in which a shift register can operate are as follows:

1) Serial input serial output 2) Serial input parallel output

3) Parallel in serial out 4) parallel in parallel out

1)Serial input serial output





2) Serial input parallel out

*In this operation the data is entered serially and taken out in parallel.

*That means first the data is loaded bit by bit . The outputs are disabled as long as the loading is taking place.

* As soon as the loading is complete , and all the flip-flops contain their required data, the outputs are enabled so that all the loaded data is made available over all the output lines simultaneously .

* Number of clock cycles required to load a four bit word is 4.Hence the speed of operation of SIPO mode is same as that of SISO mode.

3) Parallel in parallel out

* In this mode , the bits are entered in parallel i.e. simultaneously as shown in fig.

* The circuit shown is a four bit parallel input serial output register

*The binary input word B0 ,B1,B2,B3 is applied through the same combinational circuit .

* There are two modes in which this circuit can work namely shift mode or load mode.



Load mode: When the shift line is (0)low , the AND gates 2,4 and 6 become active. They will pass ,B1,B2 and B3 bits to the corresponding flip-flop.

*On the low going edge of clock, the binary inputs B0 ,B1,B2,B3 will get loaded into the corresponding flip-flop. Thus parallel loading takes place.

Shift mode: When the shift/ load line is high (1), the AND gate 2,4,6 becomes inactive. Hence the parallel loading of the data becomes impossible .

* But the AND gates 1,3 and 5 become active. Therefore the shifting of data from left to right bit by bit on application of clock pulses .

* Thus the parallel in serial out operation takes place.

4) Parallel in parallel out

* The 4 bit binary inputs B0 ,B1,B2,B3 is applied to the data input D0,D1,D2,D3 respectively os the four flip flops.

*As soon as a negative clock edge is applied , the input binary bits will be loaded into the flip- flop simultaneously.



*The loaded bits will appear simultaneously to the output side. Only one clock pulse is essential to load all the bits.

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Q5)

a)What are the advantages of VHDL. Write VHDL program for full adder.

Ans: Advantages:

1) World Wide popularity

2)VHDL supports the different types of modeling

*Structural

* Dataflow

*Behavioral

*Mixed

3) VHDL can be used at different complexity levels from single transistor up to complete systems and everything remains in the same simulation environment.

4)The language supports the flexible design methodologies top down, bottom up or mixed.

5) The language can be used as communication medium between the different CAD and CAE tools.



6)The language supports hierarchy that is digital system can be modeled as a set of interconnected components or subcomponents .

7)It supports both the synchronous and asynchronous timing models

8) Test benches can be written using the same language to test other VHDL models.



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(b)Design 4 bit synchronous up counter using T-FF.

Ans: N.A

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(c)Draw the circuit of JK –FF using NAND gate and write the truth table.

Ans;





Q6)

(a) Design on Astable multivibator using IC 555 timer to generate an output of 1 KHz with 60% duty cycle.

Ans: Note: similar



(b) Draw the circuit diagram of regulated power supply to produce output voltage of + 5 V .

Ans:

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(c) Draw drain characteristics of n-Channel JFET and explain various regions.

Ans:





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(d) What is Excess 3 code? Why it is called self complementary code?

Ans:

It is an important BCD code , is a 4 bit code and used with BCD numbers To

convert any decimal numbers into its excess- 3 form ,add 3 to each decimal digit

and then convert the sum to a BCD number As weights are not assigned, it is a

kind of non weighted codes.

The key feature of the excess-3 code is that it is self-complementing. This means

that the 1's complement of an excess-3 number is the excess-3 code for the

9'scomplement of the corresponding decimal number. Such codes have the

property that the 9’s complement of a decimal number is obtained directly by

changing 1’s to 0’s and 0’s to 1’s (i.e., by complementing each bit in the pattern).

For example, decimal 395 is represented in the excess‐3 code as 0110 1100 1000.

The 9’s complement of 604 is represented as 1001 0011 0111, which is obtained

simply by complementing each bit of the code (as with the 1’s complement of

binary numbers).

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Solution for Analog and Digital Circuits - · PDF fileSolution for Analog and Digital Circuits ... design a 8 bit Comparator using IC 7485 ... Draw the circuit of JK –FF using NAND