Variability and Reliability Aware Design for Emerging System-on-Chips

2015. 09. 01

Yongchan Ban, Ph.D.

Principal Engineer, yc.ban@lge.com

System IC R&D, LG Electronics

0

제16회 한국테스트학회 Tutorial

Outline

SoC and Embedded Systems

Technology Scaling: Variability, Reliability, Energy

Variability-aware Design

Reliability-aware Design

Power-aware Design

1

System-on Chips

2

Today’s IT (Focus on Person)

Real-time Model of the World

Global Intelligence

Future Technology

Cyber-physical System

The Internet of Things

Research Agenda

Tomorrow’s IT (Focus on Objects/World)

Public/Social Issues

Applications

Research Devices (System on Chips)

[ slide source: Prof. Jaeyong Jung ]

Technology Scaling in Every 2 Years

32 nm

2009

90 nm

2003

45 nm

2007

65 nm

2005

22 nm

2011

[ picture source: Intel ]

14 nm

2013

3

1st Gen FinFET 2nd Gen FinFET HKMG/Gate Last 2nd Gen HKMG Strain/Stress

To Go Out ~ 10 Years

4

[ picture source: Intel ]

30 Years of Scaling

Rice – single grain

Intel Atom™ - dual-core

[ source: Intel, Synopsys Forum’11 ] 5

Goals of Technology Scaling

Design new devices to be:

– Faster?

– Smaller?

– Lower power?

– Add new features?

Growth of semiconductor industry has been fueled by

the “ever cheaper” transistor

Two major issues confront further scaling

– Energy consumption!!

– Variability and Reliability!!

6

Component of Variations

Total Variation

– Systematic Variation

– Random Variation

Variation Sources

– Due to lithography, mask alignment,

etching, CMP, deposition, implant,

doping profile, temperature, etc.

Systematic Variation

– Deterministic

– Depending on layout density,

orientation, and/or location

Random variation

– Due to random process variations

– Due to fundamental randomness

Lithography Etch Loading

CMP Dishing & Erosion

Random Dopant LER Grain Boundary

7

Lithography Systematic Variation

8

Lithography Lithography

[ Source: TI ]

Line-end shortening ∆CD Proximity Poly Corner Line-edge Roughness Active Corner

Systematic Variation-aware Design: PO/OD

Line-end

Shortening

Active

Corner Rounding

Poly Corner

Rounding

Process Variation

9

Impact of Gate Length Variation

ΔLgate is up to 10% @45nm node.

The small improvement of ΔLgate reduction can leads to significant

decrease of delay and leakage variations.

-10 -8 -6 -4 -2 0 2 4 6 8 10-30

-20

-10

0

10

20

30

NMOS

PMOS

De

lay V

aria

tio

n (

%)

Length Variation (%)

-10 -8 -6 -4 -2 0 2 4 6 8 10

10-1

100

101

102

NMOS Leakage

Leakage V

ariation (

%)

Length Variation (%)

Over 20%

40X

[Ban et al., ISPD 2010] 10

Total Sensitivity based Optimization

11

Non-Rectangular Gate-aware Cell Charac.

PMOSNMOS PMOSNMOS

PM

OS

NM

OS

PM

OS

NM

OS

[ Source: TI ]

Total Sensitivity = Circuit Criticality + Manufacturability [Ban et al., ISPD 2010]

Systematic Variation-aware Design: S/D Cnt

The S/D contact resistance is as much as 26% of the gate channel

resistance at 45nm node devices.

12

[ITRS 2007]

n+

Gate Source Drain

n+

Rco

Rchannel

Rco

contactchannel

dSat

ddon RR

I

VR 2

13

Impact of Contact Variation

S/D Contact Size (CD)

– ΔS/D contact area Δcontact resistance (Rco) Δcurrent (Ids).

– 32nm standard cell (nominal CD = 40nm).

– 10nm Contact ΔCD up to 5% ΔIds & over 100% ΔRco.

30 40 50 60-10.0

-7.5

-5.0

-2.5

0.0

2.5

5.0

I ds C

urr

ent

Va

ria

tio

n (

%)

S/D Contct CD (nm)

30 40 50 60-80

-40

0

40

80

120

160

200

Rco R

esis

tan

ce

Va

ria

tio

n (

%)

S/D Contct CD (nm)

PO

LY

PO

LY

[Ban et al., DAC 2010]

14

Impact of Contact Distance on Ids

S/D Contact Position

– The Ids degrades as contacts are placed closer to the gate.

– Neighboring contact holes locally relax the strain in channel.

– Generate Look-up table for Distance weighting factor (wD)

PO

LY

50 100 150

-4

-3

-2

-1

0

1

2

3

I ds C

urr

ent

Va

ria

tio

n (

%)

Gate to Contact Space (nm)

[Eiji Morifuji, IEEE TED’09]

[Ban et al., DAC 2010]

15

Impact of Contact Shape on Ids

S/D Contact Shape

– As the contact length is larger, the Ids is increased.

– Less current crowding from the S/D electric field.

– Generate Look-up table for Shape weighting factor (wS)

40 60 80-1.0

-0.5

0.0

0.5

1.0

I ds C

urr

ent V

aria

tion

(%

)

Contact height (nm)

ACTIVE PO

LY

ACTIVE PO

LY

[Ban et al., DAC 2010]

16

Equivalent S/D Resistance Model

There are two look-up tables for a new contact model

– Distance weighting factor (wD) due to stress

– Shape weighting factor (wS) due to the current crowding

– Given ith slice of a contact,

the resistance is

where ρ is resistivity and A is

the area of a slice

– The driving current is

– The lower ω, the higher R and the smaller Ids.

ii,Si,D

iAww

R

i

iiSiD

i icodsch

ds

tot

ds AwwRRRR

V

R

V,,ds

111I

Dw

POLY SwContact

[Ban et al., DAC 2010]

Compact S/D Resistance Model

17

Contact Area Contact Position Contact Shape

0 50 100 150 200

-4

-3

-2

-1

0

1

2

3

TCAD

Proposed Model

Conventional

I ds C

urr

en

t V

ari

atio

n (

%)

Gate to Contact Space (nm)

20 40 60 80-1.0

-0.5

0.0

0.5

1.0

TCAD

Proposed Model

Conventional

I ds C

urr

en

t V

ari

atio

n (

%)

Contact Length along Gate (nm)

20 30 40 50-20

-15

-10

-5

0

5

TCAD

Proposed Model

Conventional

I ds C

urr

ent V

ari

atio

n (

%)

Contct CD (nm)

[Ban et al., DAC 2010]

S/D Contact Layout Optimization

Variability-driven Design – The main goal is to minimize the contact CD variation between the fastest

and slowest process corners.

Performance-driven Design – The contact CD increases as the pitch decreases.

– We can make vertically long contacts by reducing the space between contacts.

18

POLY METAL

ACTIV

E

POLY METAL

ACTIV

E

POLY METAL

ACTIV

E

Conventional Variability-driven Performance-driven

[Ban et al., DAC 2010]

Line-Edge Roughness (LER)

What is LER (Line Edge Roughness)?

– Random variation of MOS gate length along the gate width.

– LER is formed in the acid generation, the acid diffusion and development process.

Why LER becomes so critical

– LER does not scale accordingly and becomes an increasingly larger fraction.

– Below 30 nm the LER takes over and becomes the dominant fluctuation source.

19

Gate Length

[Chandhok, SPIE’07]

Exposure Development

[Namatsu, JVST’98]

[Asenov, IEEE TED’03]

Random Variation-aware Design on Std. Cell

Line-edge Roughness and Contact-edge Roughness

Gate Length

5.0222

2

21

2)(

c

cLER

Lf

LfS

Power Spectral Density (PSD) LER Modeling

Line-edge Roughness (LER)

[Ban et al., SPIE 2010]

[Ban et al., JETCAS 2011] [Ban et al., DAC 2011] [Ban et al., JM3 2010]

• Distance weighting factor (wD) due to stress

• Shape weighting factor (wS) due to the current crowding

Contact-edge Roughness Modeling

ii,Si,D

iAww

R

Contact-edge Roughness (CER)

20

LER-aware Poly Pitch Optimization

21

60 80 100 120 140 1603

4

5

6

7

8

9

3 L

ER

[n

m]

Poly-to-Poly Space [nm]

design

violation

process

violation

Data

Polynomial Fit

Linear Fit

5.0222

2

21

)(2)(

c

c

Lf

LxfS

3

22

11

0

)(

,...,0,)(

x

x

x

NixaxN

i

i

i

where,

or,

if

if

if

𝑥 ≤ 𝑥𝑝1

𝑥 ≥ 𝑥𝑝1

𝑥 ≥ 𝑥𝑝2

𝑃 𝑥𝑝1 𝐷 𝑥𝑝2 𝑥 > 𝑃, where 𝑃 is process violation

𝑥 < 𝐷, where 𝐷 is design violation

[Ban et al., DAC 2011]

LER-aware Poly Optimization

22

• N: a positive integer

• dj: distances from the edge

• Ψ: device criticality

[Ban et al., DAC 2011]

Cu erosion and dishing change R & C variation timing/power

Topographic variation translates to focus variation for imaging of

subsequent layers depth-of focus manufacturability

CMP impacts both IC parametric and manufacturability

CMP Induced Process Variation

[figures: Prof. Boning,MIT] Cupper Interconnect Problem

Multilevel Process

[Ban et al., KCS 2015] 23

CMP variation is highly dependent upon metal density

and pitch (line width & line space).

Dummy metal fill (conventional)

Pattern Dependent Effect

[figure: Prof. Boning,MIT]

Active Interconnect

Dummy Metal

[Ban et al., KCS 2015] 24

But, The CMP Variation is Still Huge

The dummy metal fill approach just cares for metal

layout density.

– Layout density variation is still huge.

– Layout density is not an only parameter controlling CMP.

– CMP variation mismatch and impact (e.g., 10%↑ ΔTcu @28nm)

28nm M4 Layout Density 28nm M4 Cu Thickness due to CMP

[Ban et al., KCS 2015] 25

Systematic Variation-aware Design on IP/Chip

LDE (Layout Dependent Effect)

Length of Diffusion

Well Proximity Effect Metal Boundary Effect Dual Stress Liner

[Ban et al., SPIE 2014] 22% Delay and 31% Leakage Spreading in 16nm Library

26

Variability Analysis Summary

LEA variability analysis was used to:

– Quantifies the delay and

leakage variability spread

– Verify the characterization

context positioning

– Help improve design

methodology

MUX2D0

Cell Under Test

F

I

L

L

2

F

I

L

L

2

I

N

V

D

0

SDF0

Latch

SDF0

MUX2D0

Cell Under Test

TAP

CELL INVD2

AOI22

MUX2D8 DFFD2

Fast Context Slow Context

Up to 21ps or 22% delay spread Up to 111pW or 31% leakage spread

Characterized

delay

Characterized

leakage

27 [Ban et al., SPIE 2014]

Variability-aware Implementation

Reducing Variability of Cells/IPs

– Quantify LDEs related variability in Std. Cells and Ips

– Pin point root causes of excess variability and optimize cells

Variability-Aware Placement

– Context library litho/stress simulation and analysis with LEA

– A variability score for cell combinations (CCI)

– Use cells with low variability score

Timing Margin Tuning

28 [Cadence, CDNLive’09]

Layout Guidelines to Mitigate LDEs

Avoid functional cells on boundaries

– Functional cells should be avoided on the block periphery

– Block periphery should be padded with the non-functional cells (e.g., fillers, decaps,

endcaps, and so on.).

Fix context of clock cells

– Surround all instances of clock cells with an identical context and characterize the

clock cells with the context.

– Minimizes impact of the un-modeled LDEs on the clock cells.

Surround double-height cells with non-functional single-height cells

– Double-height cells can cause high LDEs around them.

– Placing non-functional single-height cells around double-height cells reduces LDEs

on nearby functional cells.

Avoid very small drive strength cells on critical paths and clocks

– Small drive strength cells are more susceptible to LDEs.

[Freescale, SPIE 2012]

29

Routing: a key stage for printability optimization

– Last major design stage

– Wire embedding step

Lithography Aware Routing

– OPC Friendly Detailed Routing [Huang+ DAC’04]

– Multi-level Routing with OPC [Chen+ ASPDAC’05]

– RADAR: Litho-Aware Routing [Mitra+ DAC’05]

Layout Chip

Pass

Many Rerouting

ORC (check)

Systematic Variation-aware Design on Routing

Fail!!

30

Systematic Variation-aware Design on Routing

Lithography-friendly Detailed Routing

D D D

D=2 D=3

Fre

quency

Total EPE

OPC & Simulation

N-th set of Weak Pattern OPC & Simulation

D=1 D=2

Fre

quency

Total EPE

[Lin, Ban, Pan, and Li, ICCAD 2011] [Cho, Yuan, Ban, and Pan, TCAD 2009] [Cho, Yuan, Ban, and Pan, DAC 2008]

31

In-design DFM w/ Pattern Matching

[courtesy of Synopsys]

32

LGE In-Design DFM Approaches

(1) Conventional Litho. Check at the signoff stage

(2) In-design Pattern Matching from an early stage of routing

(3) Correct-by-construction Routing

Final GDS Litho. Check Hot Spots Routing Tool

Fixing DFM Clean

Routing DB Pattern

Matching Hot Spots Routing Tool

Fixing Litho. Check

Pattern Lib. Routing w/

Concur. Fix Litho. Check

Flow Runtime (sec) # Hot spot

remaining Litho. sim Pattern Match Fixing Overall

(1)Conv. DFM sign-off 57,120 487

(24 violations) 1903 59,510 0

(2)In-design DFM - 499

(49 violations) 2402 2,901 0

TAT reduction - 0.97 0.79 X 20.5

< 16FF CA57 CPU >

[Shin, Ban et al., SPIE 2014] 33

The Evolution of Pattern Matching

// Sample DRC Rules File AND poly diff gate NOT diff gate srcdrn WIDTH diff LT 5 OUT w5001 30 3 EXT[H] diff LT 5.5 OUT x5002 31 4 WIDTH poly LT 4.5 OUT w5003 32 EXT poly LT 4.0 OUT x5004 33 EXT poly srcdrn LT 2.0 OUT x5013 41 EXT[T] poly diff LT .001 OUT x5013 42 WIDTH srcdrn LT 5.5 OUT w5013 42 WIDTH gate LT 5.0 OUT w5016 45 WIDTH epi LT 7.0 OUT w5020 52 4 ENC[T] diff poly LT 4.0 OUT e5301 57 7 ; PREPARE FOR NODAL SPACING CHECK ; FLATTEN POLY LAYER FOR CONNECTION FLATTEN poly fpol ; FLATTEN SRCDRN LAYER ALSO FLATTEN srcdrn fsd ; FLATTEN SRCDRN LAYER ALSO FLATTEN epi fepi }

Classic DRC Code

Classic Pattern Matching

is a specific physical

representation

New representation is

Topological “Squish” Pattern

<rule>

<rulename>Hook.with.notch.M2</rulename>

<report merged_overlay_layer="15.102"/>

<pattern_def x_deltas="1 50 50-150 50 1"

y_deltas="1 0-100 50-100 0-500"

signature="L1

0 0 0 0 1/

0 0 1 0 1/

0 0 1 0 0/

1 0 1 0 0>

<pattern sel="15.0" />

<overlay_scanline_range>x1 x4 y1 y4</overlay_scanline_range>

</pattern_def>

</rule>

[Ban et al., SPIE 2014] 34

Topological “Squish” Pattern

Very simple Pattern Abstraction

More like DRM than DRC Rules

Easy to maintain

Natively supports all orientations (mirror, rotations)

Support multi-level patterns

High performance search engine

[Ban et al., SPIE 2014] 35

In-design DFM Optimization

36 [Source: Cadence]

Lithography Challenges in sub 45nm

k1: lithography difficulty NA: numerical aperture λ: wavelength of source HP: min. printable half pitch NA

kR

1

[S. Borkar, 2014]

37

Why Double Patterning?

Too hard with the current infrastructure!

– Increase NA (3rd generation fluid >1.4, larger lens)

– Use shorter wavelengths (13.5nm-EUV)

Have no choice but to bear with the current state, but

increase HP to print 32/22nm designs

– Double patterning!

– Reuse the current infrastructure

NAkR

1

Ex) λ = 193nm NA = 1.4 K1 = 0.26 R = 35.8 Around pitch 70nm ↓ is

a lithography limit.

Pitch

R

38

Double Patterning Tech (DPT)

Conventional LELE (litho-etch-litho-etch) DPT

stitch

stitch

(1) target (2) core mask (3) sidewall spacer (4) trim mask

Spacer Type SA (self-aligned) DPT

[Ban et al., DAC 2011] 39

Layout Decomposition vs. 2-coloring

Layout decomposition for DPT is more complex than

phase assignment or 2-coloring

A

B C

D

E

A A

B

C D

E

A B

C D

E

Uncolorable

A

B C

D

E

A

B C

D

E

Stitch

[Cho, Ban, ICCAD’08]

A B

C D E

40

LELE DPT Aware Routing

a) # of stitches b) wirelength, via, and so on

[Cho, Ban, ICCAD’08] 41

SADP Aware Routing

SADP Layout Decomposition

SADP-awra Routing

[C. Kodama+, ASPDAC’13]

[Ban et al., DAC 2011]

42

Reliability Problems in 3D ICs

Mainly due to CTE (coefficients of thermal expansion) mismatch

between Si and Cu TSV

[ Prof. S. Lim, Gatech ]

Better Performance

Massive Bandwidth

Reduced Interconnect Delays

Power Reduction (Less IO driver)

Higher Functionality/Space

Heterogeneous Integration

43

TSV-TSV & TSV-Transistor Interactions

[ Source: IMEC ]

44

Keep-Out Zone (KOZ)

KOZ tradeoff: area vs delay vs reliability

[ Prof. S. Lim, Gatech ]

45

TSV Stress Impact on Mobility

Hole Mobility Variation Electron Mobility Variation

Thermal Mechanical Stress

[ D.Pan, ASPDAC’12 ]

46

TSV Stress-aware Placement

[ K.Athikulwongse, ICCAD’10 ]

Hole Mobility Variation Electron Mobility Variation

Hole Critical Cell

Electron Critical Cell

Regula

r TSV

Irre

gula

r TSV

47

Reliability-aware Design (EM)

Signal Electro-migration (EM)

– Mean-to-time-failure (DC Current)

– Mean-to-time-failure (AC)

– Mean-to-time-failure (AC+ΔProcess)

– Joule Heating, Signal interconnects

– Prone to process variation (lithography, etch and CMP)

– Higher driving strength in FinFET and higher circuit frequency

void

hillock

/kT)(E

nACae

JJ

A=MTTF

/kT)(E

nprocess)AC(ae

JJJJ

AA=MTTF

[Ban et al., SPIE 2014]

Failures due to Electromigration

[Ban et al., KTC 2014] 48

/kT)(E

nae

J

A=MTTF

Signal-EM in 16nm Design

(a) When the impact of the

geometry is higher than

one of the current

density, MTTF

increases.

(b) While when the impact

of the current density is

higher than one of the

geometry change, MTTF

decreases.

/kT)(E

nprocess)AC(ae

JJJJ

AA=MTTF

[Ban et al., SPIE 2014] 49

Signal-EM with Input Voltage

Front-end: Typical process corner

Back-end: 110 ℃ and RCbest parasitic corner

The higher deriving current from FinFET causes more EM

violations.

1 6

13

31

54

94

0

20

40

60

80

100

0.72 V 0.8 V 0.88 V

# o

f EM

Vio

lati

on

s

Input Voltages

# of Signal-EM w/ Input Voltage

@Irms @Iavg

101% 113%

124%

189% 211%

232%

0%

50%

100%

150%

200%

250%

300%

0.72 V 0.8 V 0.88 V

Max

. EM

Vio

lati

on

s

Input Voltages

Max. Signal-EM w/ Input Voltage

@Irms @Iavg

[Ban et al., KTC 2014] 50

Signal-EM with Ambient Temperature

12 12 13 15

86 86 94 97

0

20

40

60

80

100

120

-40 ℃ 0 ℃ 85 ℃ 125 ℃

# o

f EM

Vio

lati

on

s

Ambient Temperature

# of Signal-EM w/ Ambient Temp.

@Irms @Iavg

123% 123% 124% 125%

232% 232% 232% 232%

0%

50%

100%

150%

200%

250%

300%

-40 ℃ 0 ℃ 85 ℃ 125 ℃

Max

. EM

Vio

lati

on

s

Ambient Temperature

Max. Signal-EM w/ Ambient Temp.

@Irms @Iavg

Front-end: FF (Fast-Fast) process corner

Back-end: 110 ℃ and RCbest parasitic corner

The more FinFET current is induced as temperature increases

due to temperature inversion.

[Ban et al., KTC 2014] 51

Signal-EM with Metal Temperature

1

13 13 13

94

1000

1

10

100

1000

85 ℃ 110 ℃ 125 ℃

# o

f EM

Vio

lati

on

s

Metal Temperature

# of Signal-EM w/ Metal Temp.

@Irms @Iavg

112% 124% 124% 124%

232%

647%

0%

100%

200%

300%

400%

500%

600%

700%

85 ℃ 110 ℃ 125 ℃

Max

. EM

Vio

lati

on

s

Metal Temperature

Max. Signal-EM w/ Metal Temp.

@Irms @Iavg

Front-end: Typical process corner

Back-end: 110 ℃ and RCbest parasitic corner

The signal-EM is so sensitive to the metal temperature.

110℃ is recommended for sub-20nm node design.

[Ban et al., KTC 2014] 52

Signal-EM with Metal RC Corners

6 12 11

4 4

77 86 86

77 70

0

20

40

60

80

100

Typical RCBest RCBest_D RCWorst RCWorst_D

# o

f EM

Vio

lati

on

s

Metal RC Corners

# of Signal-EM w/ Metal RC Corners

@Irms @Iavg

121% 124% 122% 120% 120%

230% 232% 232% 234% 234%

0%

50%

100%

150%

200%

250%

300%

Typical RCBest RCBest_D RCWorst RCWorst_D

Max

. EM

Vio

lati

on

s

Metal RC Corners

Max. Signal-EM w/ Metal RC Corners

@Irms @Iavg

Front-end: FF (Fast-Fast) process corner

RCBest corner gives the worst EM violation.

RC reduction on signal nets might induce more current.

The DPT corners minor changes EM violations.

**_D means DPT corner.

[Ban et al., KTC 2014] 53

Reliability-aware Design

[Ban et al., SPIE 2014]

16nm Cortex-A57 CPU

Redundant Via Metal Dummy Fill

1W

1S

2W

2S 2S

3W

Non-Default Rule

EM Fix Approaches [Ban et al., KTC 2014]

EM on Via

EM on Clock Net

54

Power Basics

The total power dissipated in a device consists of two components.

Static or leakage power is state, temperature, process and voltage

dependent.

Dynamic Power is comprised of internal power and switching power.

dynamicstatictotal PPP

leakstatic IVddP

switchingernaldynamic PPP int

clkeffdynamic fVCP 2

55

Overall Voltage drop is

In addition to IR drop, inductance for power ground network

also affects the voltage drop.

Dynamic Voltage Drop

dtLdiIRVdrop /

. . .

VDD

Time(ns)

IR-drop hot spot

[Voltage drop @ transistor level] [Hot-spot Area]

[Ban et al., ISOCC 2014] 56

Dynamic IR Drop w/ Process Corners

57 [Ban et al., ISOCC 2014]

RC corners # DVD

Max.

# DVD

Min.

Worst

Instance

Worst

Wire

RCBest_DPT 531 426 27.8% 27.0%

RCBest_dPV 712 433 29.1% 27.6%

RCBest 561 433 28.4% 27.6%

Typical 1537 513 32.9% 31.6%

RCWorst 4722 1199 40.5% 38.7%

RCWorst_dPV 2365 400 33.5% 30.5%

RCWorst_DPT 4543 1086 40.3% 38.5%

[DVD with Metal RC-corner]

Future Research Directions

Cyber-physical System

The Internet of Things

Reliable SoC/Embedded System

• Manufacturability

• Reliability

• Testability

• Energy Efficiency

Circuit/System-level Techniques for

New Processes/Devices

• Pi-gate, Wire, CNTs

• EUV, DSA, Nanowires

• Memristor-based Systems

3D SoC

• TSV (Through Silicon Via)

• Heterogeneous Integration

HW/SW Co-design

• HW Acceleration IPs

• System Software

VerificationSynthesis

Function Architecture

Hardware Software

Mapping

Re

fin

em

en

t Ab

stra

ctio

n

Abstract Co-design Process

New Devices based SoC

3D SoC HW/SW Co-design

Emerging Applications

58

Thank You!

제16회 한국테스트학회 Tutorial, LG전자, 반용찬 수석연구원