Fundamentals of PLLs (I ) - 國立中興大學cc.ee.nchu.edu.tw/~aiclab/teaching/pll/lect01_Fun1.pdf · Fundamentals of PLLs (I ) Phase-Locked Loops. PLL ICs 1-1 Ching-Yuan Yang

Ching-Yuan Yang

National Chung-Hsing UniversityDepartment of Electrical Engineering

Fundamentals of PLLs (I)

Phase-Locked Loops

1-1 Ching-Yuan Yang / EE, NCHUPLL ICs

Why phase-lock ?

CKc

Digital IC

- Jitter Supression

tT T + t1

- Frequency Synthesis

PLL

fout = 900 ~ 925 MHz( in 30 Khz steps )

- Skew ReductionCKs

CKs

CKc

tt

- Clock RecoveryFiber

Receiver

DataRecovered

clock

T + t2 T + t3

CPU MEM I/O

Experience Clock Skew

PLL

Micro-processor

t

CK


History of PLL

First PLL: 1932 by de Bellesize, Coherent communication

First PLL IC: 1965, purely analog (Linear PLL)

First Digital PLL: around 1970 (using Digital Phase Detector)

All Digital PLL: Digital Filters, NCO (Numerically Controlled Oscillator), …

Software PLL: Using DSP

1990s: Most of the PLL is Charge Pump PLL


What is PLL ?

Operates on excess phase of x(t) and y(t). Feedback system with PD as an error amplifier. “Locked” when phase difference between input and output is constant with

time.

PhaseDetector

LoopFilter

SynchronizedOscillator

Referencesignal Synchronized

signal

x(t)y(t)


Terminology

LockingWhen VCO output is in phase as well as in frequency with the referenceinput signal

Lock Range

Input frequency range over which the loop can maintain locking

Capture Range

Input frequency range onto which the loop can lock

Free Running Frequency

VCO running frequency when no input applied

Acquisition Time: Pull-in time + Settling time

Time required for the PLL to lock itself on to the reference clock

Phase Offset or Phase Error (Steady State)

When PLL is locked, the phase difference between input and output


Basic feedback network of PLL

( ) sin[ ( )] sin ( )

( ) cos[ ( )] cos ( )i i i i i i

o o o o o o

v t V t t V t

v t V t t V t

( ) ( ) ( )

sin ( )cos ( )

1sin ( ) ( ) ( ) sin ( ) ( ) ( )

2

where is the transfer constant [1/V]d m i o m

m i o i o

m i o i o i o i o i o

v t K v t v t K

K VV t t

K VV t t t t t t

( ) sin ( ) ( ) ( )

sin ( )

where [V/rad]c d i o i o d m i o

d e

v t K t t t K K VV

K t

( ) ( )e i ot t


vc(t) changes the free running frequency c of the VCO.( ) ( )

( ) ( ) ( )

sin ( )

( )sin ( )

where is designated as the oscillator gain [2 Hz/V].

where and .

o c o c o

e i c o c

i c o d e

ee i o o d

t K v t K

t t t K v t dt

t t K K t dt

d tK t K K K

dt

K is indicated as the gain of the PLL [2Hz].


Solution in the closed form

For the steady state, that is, for t , the lhs of eq. (A) equals zero with theresult

( )sin ( ) / 1e

e

d tK t K

dt

( )sin ( )e

e

d tdt

K t

10 2 2

2tan tan

4 2( )eK

t tKK

0 2 2

tan( ) tanh( )

1 ( ) /( ) tan( / 4 / 2)1ln

1 ( ) /( ) tan( / 4 / 2)( )

Since , , we have

e

e

K jx j x

K Kt t

K KK

2 201

2 20

1 exp ( ) ( )2 tan

21 exp ( ) ( )e

K t tK

K K t t

(A)

1sine K


Linearized solution

The time-dependent phase difference e(t) at the output of the PD in theclosed PLL is small and prone to the simplification

(This assumption is supported with the reality that a lot of PDs are linear ornearly linear in the working range.)

The phase difference in the steady state:

sin ( ) ( )e et t

( )( )e

e

d tK t

dt

( )

sin ( )ee

d tK t

dt

0 0( ) 0 where is the integration constant for .Kte e et e t

K K

e K


Solution in the frequency domain

In the locked state, i = o and e << /2.

Laplace transform:

PLL transfer function

0

0

( ) ( ) ( ) sin[ ( ) ( )]

( ) sin[ ( ) ( )]

o c o c o o c o c d o i o

o c o c

o i o

t K v t t K v K K t t

K v

t K t t

( ) ( ) ( )e i ot t t

( ) ( ) ( )o i os s K s s

( )( )

( )o

i

s KH s

s s K

( ) ( ) ( )1 ( )

( ) ( )i o e

i i

s s s sH s

s s s K

first order


Simplified block diagram of PLL with individual transfer functions

PD: we get a voltage vd(t) proportional to the phase difference of the inputs.vd(t) = [i(t) o(t)]Kd Kd: the phase detector gain [V/rad]

Loop filter: a low-pass filter attenuating “carriers” with frequencies i = o,and ideally all undesired sidebands. Note that the useful signal vc(t) is aslowly varying “DC” component.

vc(t) = vd(t) hf(t) hf(t): the time response of the loop filter

VCO:

In most cases, Kd and Ko are voltage-dependent. nonlinear model in PLL Its linearization, justified in small-signal cases (“steady state” working mode),

provides a good insight into the problem.

( ) ( )d d eV s K s ( )

( )

( )

i

i

i

v t

t

t

( ) ( ) ( )c dV s F s V s ( ) ( )oo c

Ks V s

s ( )

( )

( )

o

o

o

v t

t

t

( ) ( ) ( )o o c o ct t dt t K v t dt c(t): the VCO free-running frequencyKo: the VCO gain [2Hz/V]


Simplified block diagram of PLL in a feedback path

( )d oK KF s

s

( )( ) ( ) ( ) ( )d o

i o M o

K K F ss s F s s

s

( ) ( )( )

( )( ) ( ) 1 ( )1

M

M

KF s F sG ssH s

KF s F s G ss

( ) ( )( )

Forward loop gain

Open loop gain

d o

M

K K K

KF s F sG s

s


Order of PLLs

F(s) = 1 and FM(s) = 1,

The PLL is designated as the first-order loop since the largest power of s inthe polynomial of the denominator is of the order one.

Order of PLL is accordance with the order of the respective polynomial inthe denominator of its transfer function.

( )K

H ss K

( )d oK KF s

s


Type of PLLs

Introducing the gain G(s), , we get

Laplace limit theorem for the final value of e(t):

Every PLL contains at least one integrator, that is, VCO. n ≥ 1 (PLL at least type 1)

Type of PLL: no. of poles (s = 0) in G(s) no. of integrators in the loop Each integrator contributes one pole to the TF, so that (type no.) (order no.)

( )d oK KF s

s

( )( ) ( ) ( ) ( ) ( ) ( ) ande i M o o e

KF ss s F s s s s

s

1

( ) ( )1 ( )e is s

G s

( )

( )( )n

A sG s

s B s

( )( ) ( )

( ) ( )

n

e i n

s B ss s

A s s B s

1

0

( )lim ( ) lim ( )

( ) ( )

n

e i nt s

s B st s

A s s B s


Steady state errors

Phase step: The final value is zero for PLLs.

Frequency step:

In type-2 PLL with two integrators in the loop, the DC gain F(0) is very large,so Kv and consequently the steady state error is negligible.

Frequency ramp:

Type-3 PLL can eliminate even the steady state error e3 for t to zero. Frequency locked loop may be considered as type-0 PLL.

1

0

( )lim ( ) lim ( ) 1

( ) ( )

n

e i nt s

s B st s n

A s s B s

( ) ii s

s

2( ) i ii s

s s

2

1

(0)lim ( )

(0) (0) (0) : velocity error constanti i

e i vt

M vn

Bt K

A KF F K

2 3( ) i i ii s

s s s

3

2

(0)lim ( )

(0) : acceleration or dynamic tracking errori

e i at

an

Bt K

A K

1lim ( ) 0et

t


Block diagram of the first-order PLL

Open-loop transfer function (loop gain)

System transfer function

Error transfer function

( )( )

( )o d o A

e

s K K K KG s

s s s

( ) ( )( )

( ) 1 ( )o

i

s G s KH s

s G s s K

( ) ( )d d eV s K s( )

( )

( )

i

i

i

v t

t

t

AK ( ) ( )oo c

Ks V s

s ( )

( )

( )

o

o

o

v t

t

t

( )( ) 1 ( )

( )e

i

s sE s H s

s s K


Normalized transfer function of 1st-order PLL

Introducing

Normalized loop gain

Normalized transfer functions

s jjx

K K

1( )G

1( ) ( )

1 1 (Low-pass filter) (High-pass filter)H s E s

20log ( )E jx20log ( )H jx


Phase detector

A phase detector is a circuit whose average output, , is linearlyproportional to the phase difference, , between its two inputs.

In the ideal case, the relationship between and is linear, crossingthe origin for = 0.

The operation of phase detectors is similar to that of differential amplifiers inthat both sense the difference between the two inputs, generating aproportional output.

Gain KPD : the slope of the line, is expressed in V/rad.

outV

outV

Phase DetectorV1(t)

V2(t)Vout(t)

Vout

KPD


Phase detector : Multiplier

Phase Detector using Analog Multiplier

Gilbert multiplier

Output voltage dependent on the input signal amplitudes

Narrow linear range (Narrow lock range)

Cannot discriminate frequency difference

offsetedmd VVV )sin(

Vd

Vi

Vo

Vd

Vdm

e/2

/2

Vdm


Phase detector : XOR

0

00 2

2

VK

VVV

PD

out

independent of theinput frequency tVout

tV 2

tV 1

outV

2V

1V

0

outV

2V

1V

o u tV

2V

1V

2

outV

2V

1V

23

22

Vo

0

outV

Vout

V1

V2


Phase detector : XOR (cont’d)

When locked, the phase difference is 90 degree

Output voltage independent on the input signal amplitudes

Output voltage dependent on the input duty cycles

Narrow linear range (Narrow lock range) /2

Cannot discriminate frequency difference

Use for Data/Clock Recovery PLL: input noise dominant

- Hybrid PLL (Analog PLL + Digital PLL)

No Dead Zone


Conceptual operation of a phase-frequency detector (PFD)

PFDAB

A A

B B

AQ

BQ

BQBQ

AQAQ

t t

BA BA


Phase detector : PFD – three-state PD

QA = 1QB = 0

QA = 0QB = 0

A

QA = 0QB = 1

AState I State II State III

A

B B

B

A

B

QA

QB

A

B

QA

QB

A

B

QA

QB

A

B

QA

QB

State diagram

Timing diagram


Implementation of PFD

Input-output characteristic: PFD followed by low-pass filters:

AQ

BQ

A

B

outV

o360

o360


- Phase detector : PFD

When locked, the phase difference is 0 degree

Output voltage independent on the input signal amplitudes

Output voltage independent on the input duty cycles

Wide linear range (Wide lock range) 2

Discriminate frequency difference

Use carefully for Data/Clock Recovery PLL

- Hybrid PLL (Analog PLL + Digital PLL)

Dead Zone problem

Due to finite gate delay

Introduce large jitter or poor phase noise


- The width of the narrow reset pulses

A B

QA QB

QA QB

E

E

F

F

B

QB

A

QA

QB

Reset

Reset

E, F

E, F


PFD- Scheme with NAND

UP

DN

A (REF)

B (VCO)


PFD- Dynamic CMOS PFD

Kim, JSSC, May 1997

A (REF)QA (UP)

B (VCO)QB (DN)

A (REF)

B (VCO)

QA (UP)

QB (DN)

A (REF)

B (VCO)

QA (UP)

QB (DN)

Documents

Fundamentals of PLLs (I ) - 國立中興大學cc.ee.nchu.edu.tw/~aiclab/teaching/pll/lect01_Fun1.pdf · Fundamentals of PLLs (I ) Phase-Locked Loops. PLL ICs 1-1 Ching-Yuan Yang