K.#S. Lee, S. Kwon, F. Maloberti: A Power(Efficient Two ...ims.unipv.it/~franco/JournalPaper/100.pdf · Manuscript received August 30, 2006; revised January 3, 2007. K.-S. Lee is

K.-‐S. Lee, S. Kwon, F. Maloberti: "A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications"; IEEE Journal of Solid State Circuits, Vol. 42, June 2007, pp. 1206-‐1215.

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1206 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007

A Power-Efficient Two-Channel Time-Interleaved��Modulator for Broadband Applications

Kye-Shin Lee, Member, IEEE, Sunwoo Kwon, Student Member, IEEE, and Franco Maloberti, Fellow, IEEE

Abstract—A two-channel time-interleaved second-ordersigma-delta modulator for broadband applications includingasymmetrical digital subscriber line (ADSL) is presented. Theproposed two-channel �� modulator uses a single integratorchannel which does not require additional active elements forthe quantizer input generation, since the integrator outputs aredirectly used as the input of the quantizers. As a result, the entiremodulator can be implemented using only two op-amps, which isbeneficial for both power consumption and area. Furthermore,this architecture is robust to channel mismatch effects and canoperate with a simple clocking scheme. The �� modulatorachieves a dynamic range of 85 dB over a 1.1-MHz signal band-width with an effective clock frequency of 132 MHz. The circuitis implemented in 0.18- m CMOS technology using metal–insu-lator–metal capacitors. The total power consumption of the ��modulator is 5.4 mW from a 1.8-V supply and occupies an activearea of 1.1 mm2.

Index Terms—Channel mismatch, effective clock frequency,sigma-delta (��) modulator, signal bandwidth, single integratorchannel, time-interleaved (TI).

I. INTRODUCTION

RECENT broadband and wideband applications requirelarger bandwidth for the analog-to-digital converters

(ADCs), which creates limitations when using modulators[1]–[7]. In order to enlarge the bandwidth of the modulator,obviously the sampling clock frequency should increase eventhough high-order or multibit architectures are used. However,with a high sampling clock typically beyond the 100-MHzrange, CMOS implementation of the switched-capacitormodulator is problematic due to the high-frequency limitationsof the op-amps and the sampling switches [8]. Furthermore,along with the large-signal bandwidth, low power consumptionis required for both battery-operated wireless handsets andwireline applications such as ADSL [2], [6]. This is criticalfor longer battery operation time and excess heat removal forthe equipment, which makes the circuit design much morechallenging.

The time-interleaved (TI) modulator can be a good solu-tion for this problem, since the signal bandwidth of the modu-lator can be simply extended by adding more channels instead

Manuscript received August 30, 2006; revised January 3, 2007.K.-S. Lee is with Texas Instruments Inc., Dallas, TX 75243 USA (e-mail:

[email protected]).S. Kwon is with the School of Electrical Engineering and Computer Science,

Oregon State University, Corvallis, OR 97005 USA.F. Maloberti is with the Department of Electronics, University of Pavia,

1-27100 Pavia, Italy.Digital Object Identifier 10.1109/JSSC.2007.897151

of increasing the sampling clock frequency [9]. So far, a numberof TI schemes for modulators that focus on overcomingthe difficult conversion steps to obtain proper TI structures havebeen proposed [9]–[11]. However, even though the two-channelTI modulator is the simplest form, the circuit-level implemen-tation using the above approaches still has drawbacks due toseveral practical limitations that are discussed in the followingsections. Furthermore, time-interleaving does not always reducethe power consumption of the modulator due to the in-creased number of active components. The above issue moti-vates the development of TI modulators that leads to simplecircuit implementation, low power consumption, and high areaefficiency.

The solution proposed in this paper is a simplifiedtwo-channel TI second-order architecture that can beimplemented by using only two op-amps. As a result, the powerconsumption and area can be reduced by the combination ofthe two factors. The first factor is innate for the TI nature whichalleviates the speed limitation of the modulator by enablingthe internal blocks to operate at half of the effective clockfrequency. The second factor is the reduced number of activecomponents, which is due to the simplified structure. Section IIrecalls the conventional TI approach for modulators withthe practical limitations. The proposed two-channel TI archi-tecture is described in Section III. In Section IV, the effect ofmajor nonidealities is discussed. The circuit implementationand measurement results are covered in Sections V and VI,respectively. Finally, the conclusion is given in Section VII.

II. TWO-CHANNEL TI MODULATOR

A. Basic Concept

Fig. 1(a) shows the block diagram of the two-channel TI ADCthat includes the input sampler, internal channels, and the outputmultiplexing block. In addition, the corresponding input/outputtiming is described in Fig. 1(b). At instant , the sampledinput and the previous input are decimated bythe input sampler, which generates the two inputs and foreach channel. The decimated signals and are equivalent to

and , respectively. Furthermore, the two channeloutputs and are simultaneously generated. Noticing thatthe internal channels of the TI ADC operates at half of the inputsampling rate, the channel outputs are represented as the dec-imated signals and . The final output is ob-tained by simply multiplexing the two channel outputs, whichis equivalent to up sampling and summation. As a result, thetwo-channel TI ADC takes two inputs and andgenerates the corresponding outputs and simulta-neously. Assuming that each channel operates with a clock rate

0018-9200/$25.00 © 2007 IEEE

LEE et al.: POWER-EFFICIENT TWO-CHANNEL TIME-INTERLEAVED MODULATOR FOR BROADBAND APPLICATIONS 1207

Fig. 1. Two-channel TI Nyquist-rate ADC. (a) Block diagram. (b) Input/outputtiming.

of , the effective clock rate of the two-channel TI ADCbecomes . This doubles the signal bandwidth of theADC as far as the oversampling rate is unchanged, since

.

B. Practical Limitations

The basic concept of the TI ADC can be applied to mod-ulators. However, the difficulty of converting a modulatorinto its equivalent TI structure originates from the recursiveoperation of the modulator [10]. This requires generatingthe complete feedback signals as well as the integrator out-puts, which makes it more complicated with respect to theTI Nyquist-rate ADCs [12]. In addition, channel mismatchand quantizer domino critically limit the practical circuitimplementation.

Quantizer domino is a delay-free path connecting a certainquantizer output to another quantizer input via the analog blockswithout passing through a delay [11]. This occurs in the two-channel TI modulator when the second channel output

is generated [see Fig. 1(b)]. Since is obtained by quan-tizing a certain integrator output which requires the first channeloutput to be completely determined. This ismainly due to the recursive operation of the modulator,which the previous output of the modulator is always neces-sary in obtaining the present output of a certain integrator. Fig. 2shows the quantizer domino in the two-channel modulator.With the quantizer domino, switched-capacitor (SC) implemen-tation of the TI structure is not feasible, since the valid output ofquantizer is required for the input of quantizer in a situa-

Fig. 2. Quantizer domino in two-channel TI �� modulator.

tion where the two quantizer outputs and should be gener-ated at the same time. Channel mismatch in TI modulatorscan increase the in-band noise level and cause tones that fallwithin the signal band [9], [10]. In particular, the mismatcheswithin the global feedback paths are critical, since they gen-erate nonnoise-shaped error terms at the output of the modu-lator, which directly affects the in-band noise power.

C. Conventional Approaches

Among the TI approaches for modulators, only theblock digital filtering method [9] and the output predictionscheme [11] lead to feasible circuit level implementation ofthe two-channel TI modulator. In Fig. 3(a) and (b), theblock diagram of the two-channel TI modulator based oneach approach is described as Type-I and Type-II, respectively.In Type-I, basically two integrator channels are used. Thecross-coupled path represents the integrator output within eachintegrator channel that feeds to the other channel, which isused as the input of another integrator. However, to avoid thequantizer domino, the sampling and summing operation ofthe upper and bottom integrator channels should have a halfclock difference. This complicates the entire control clockingscheme of the modulator due to half clock delays. Furthermore,the mismatch between the two global feedbacks ( and

path) can be problematic, which needs an additionalcompensation scheme.

Type-II uses an incomplete integrator output for the inputof the second quantizer in order to eliminate the quantizerdomino. Incomplete integrator output is the complete integratoroutput without the modulator output terms [11]. In addition,this structure is less sensitive to channel mismatch due to thesingle global feedback path. However, the drawback is thelarge number of levels for the second quantizer and the globalfeedback DAC. This is due to the increased swing range of theincomplete integrator output term used for the second quantizerinput. Moreover, in order to generate the incomplete integratoroutput, possibly an additional active component is requiredat the input of the second quantizer, which complicates thepractical implementation.

III. PROPOSED ARCHITECTURE

Here, we describe how the conventional single-loopsecond-order modulator is transformed into the proposedtwo-channel TI structure. Following, the proposed architectureis compared with other two-channel TI modulators.

A. Two-Channel Second-Order Modulator

The proposed architecture is a modified version of Type-IIshown in Fig. 3(b). However, the improvement of the proposed


Fig. 3. Two-channel TI �� modulators. (a) Type-I: block digital filteringmethod. (b) Type-II: output prediction scheme.

Fig. 4. Conventional second-order �� modulator.

solution is using a different incomplete integrator output formand an additional modification, which leads to a more simpli-fied way of generating the second quantizer input as well as theglobal feedback signal.

Fig. 4 shows the conventional second-order modulatorwhere and represent the output of the first andsecond integrators, respectively. In this case, only one outputis generated for each time slot by quantizing the output of thesecond integrator, that is,

(1)

For the equivalent two-channel TI modulator, the two outputsand , which each correspond to the outputs

and of the conventional second-order modulator,should be generated at the same time. Obviously, the outputsof the two-channel TI modulator and will be thequantization results of the first and second quantizers and

, respectively. We begin with obtaining the integrator outputthat is used for the input of the first quantizer . We considerthe first and second integrator outputs of Fig. 4, which can beeach written as

(2a)

(2b)

The integrator outputs and for the two-channel TImodulator that each correspond to andof (2a) and (2b) are given as

(3a)

(3b)

where the input is equivalent to . However,two simplifications are made when converting (2a) and (2b) into(3a) and (3b). First, the decimated input term is notused in (3a) and (3b), which is eventually removing an outputbranch of the input sampler at the first integrator input. This issimilar to the zero insertion interpolation technique proposed in[10], where the performance of the TI modulator will notbe degraded by losing the input signal components as far as theOSR is larger than the total number of channels. Therefore, theimplementation of the input sampler can be simplified, sinceit does not need to operate with a higher clock rate than theinternal channels. Second, the input term is notincluded in (3b). As a result, the feedforward path connectingthe output of the input sampler to the second integrator inputwill not be present in the proposed structure. However, unlikeremoving the feedback terms of an integrator, simply getting ridof one feedforward input will not affect the overall stability ofthe modulator. Instead, this will reduce the output swing of thesecond integrator, which can eventually decrease the number oflevels for the quantizer and the local feedback DAC, connectedto the output of the second integrator.

Based on (1), the first output of the TI modulatoris obtained by quantizing the integrator output given in(3b), that is,

(4)

Furthermore, to obtain the second output , we take a lookat the successive second integrator output of Fig. 4, which isgiven as

(5)

Now, the successive integrator output of the two-channel TImodulator corresponding to is written as

(6)

where and are the outputs of the integratorchannel given by (3a) and (3b), and is the first modulatoroutput. However, directly using (6) for the input of the secondquantizer will lead to quantizer domino due to the output term

. Therefore, in the proposed architecture, the incompleteintegrator output is used as the input of the secondquantizer , that is,

(7)


Fig. 5. Proposed two-channel second-order TI �� modulator.

TABLE ICIRCUIT COMPLEXITY OF TWO-CHANNEL TI �� MODULATORS

The incomplete output (7) does not include the first modulatoroutput term or even the second integrator output term

existing in (6). As a result, the first integrator outputis directly used as the second quantizer input. This

eliminates the analog summing block used for the two-channelsecond-order modulator in [11], which will eventuallyreduce the number of levels for the second quantizer andthe global feedback DAC. Furthermore, using (6), (7) can berewritten as

(8)

Noticing , and using (4), the quantizationof (8) leads to the incomplete second modulator output, whichis given by

(9)

It is shown that the incomplete output is a sum of the completefirst and second outputs. Therefore, the complete second output

can be simply obtained by subtracting from (9), inthe digital domain.

Fig. 5 shows the block diagram of the proposed two-channelTI second-order modulator where path-1 and path-2 areboth removed. The integrator channel is implemented by (3a)and (3b). In addition, as derived, the output of the first integratoris directly connected to the input of the second quantizer .This simplifies the global feedback path, since, based on (9), theoutput of can be used as the global feedback signal. The localfeedback is to implement the additional term in(3b). Furthermore, this approach can be applied to four-channelTI modulators [13].

B. Comparison With the Previous Approach

Table I shows the circuit complexity of the two-channel TImodulators. Each structure is assumed to be an equivalent

two-channel version of the conventional second-order

modulator with a five-level quantizer (Fig. 4). For Type-I,the number of levels for the quantizers and DACs are all fivelevels, but requires four op-amps for the actual implementation.Type-II can be implemented using three op-amps, but needseleven levels for the second quantizer and seven levels for theglobal feedback DAC. However, the proposed structure requiresfewer levels for the quantizers and DACs due to the previouslymentioned simplifications and can be implemented with onlytwo op-amps, since no active component is needed for thesecond quantizer input generation. Therefore, the additionalcircuitry compared with the conventional second-ordermodulator is the low-resolution quantizer and the localfeedback DAC which are all three levels. In addition, the entireblock can operate with the conventional two phase clocks,which does not complicate the control clocking scheme.

IV. EFFECT OF NONIDEALITIES

A. Ideal Modulator Performance

The transfer function of the proposed two-channel TImodulator shown in Fig. 5 is obtained from the -domain rep-resentation of the first and second outputs

(10a)

(10b)

where and are the quantization errors of the quantizersand , respectively. By combining the two outputs using polyphase decomposition [14], we obtain

(11)

The final output expression is given by

(12)


Fig. 6. SNR degradation versus op-amp DC gain.

This shows that the quantization error is second-order-shaped, but, due to an extra error term , the in-bandquantization noise is doubled. This is responsible for the 3-dBSNR degradation with respect to the two-channel second-order

modulators (Type-I and Type-II) shown in Table I, as-suming that the signal bandwidth of the modulators is identical.The degradation is mainly due to removing the feedforwardpath (path-2) shown in Fig. 5, not by using instead of

as the global feedback. Therefore, the SNR improvementis 12 dB compared with the conventional second-ordermodulator shown in Fig. 4, when both modulators are operatingat the same internal clock rate . However, the 3-dB SNRdegradation is not much compared with the circuit simplifi-cation obtained in the proposed architecture. As a result, theproposed two-channel TI second-order modulator canachieve a 13-b resolution over a signal bandwidth of 1.1 MHzusing three levels and five levels for quantizers and ,respectively. This is enabled by an effective sampling rate

MHz with , whereas the internal blocksof the modulator operate at half of this rate MHz.

B. Nonideal Integrator

The nonideal integrator includes the phase error and gainerror. The finite DC gain of the op-amp is responsible for thephase error whereas the gain error is due to the coefficient mis-matches and improper settling caused by the finite GBW andslew rate of the op-amp [15]. In order to find out the degrada-tion caused by the integrator phase error and gain error, eachintegrator within the proposed two-channel modulator isreplaced with the nonideal integrator, in which the transfer func-tion is described as

(13)

where is a coefficient, is the DC gain of the op-amp, andis the integrator gain error.

Fig. 6 represents the SNR degradation with respect to theop-amp DC gain . The degradation due to the first integrator

Fig. 7. SNR degradation versus integrator gain error.

Fig. 8. SNR degradation versus channel mismatch.

phase error is much worse compared with the degradationcaused by the second integrator phase error. This can be ex-plained by the nonshaped error terms in the noise transfer func-tion of the proposed two-channel TI modulator generatedby the finite DC gain of the first integrator op-amp. However,the second integrator phase error is first-order-shaped. There-fore, in order to make the degradation negligible, the op-ampDC gain for the first and second integrators should be at least65 and 50 dB, respectively. Fig. 7 shows the SNR degradationdue to the integrator gain error. The effect of the gain error isless critical for the proposed structure compared with the phaseerror, since the gain errors of the first and second integratorsare each first- and second-order-shaped, respectively.

C. Channel Mismatch

Channel mismatch effects can degrade the performance ofmultipath TI modulators [9], [10]. However, similar to theType-II structure shown in Fig. 3(b), the proposed two-channel

modulator is less sensitive to channel mismatch effects dueto the single global feedback path. This prevents the folding of


Fig. 9. SC implementation.

quantization noise components near into signal band-width, since the two modulator outputs and will be af-fected by the same amount of feedback path error [11]. In ad-dition, the in-band noise power due the gain error of each DACis obtained from the noise transfer function including the gainerror of the DACs, that is,

(14a)

(14b)

where and are the gain errors of and dueto the component mismatches, and is the quantization noisepower of each quantizer. It is shown that the gain error of theglobal feedback DAC and the local feedback DAC

are all first-order-shaped by the loop filter operation.Therefore, the mismatch effect between and

is not as critical. An additional benefit is the single integratorchannel, which eliminates the possibility of the mismatcheffects among multiple integrator channels mainly caused bythe nonuniform phase error and gain error of the integratorswithin the internal channels. Furthermore, using two multibitquantizers is not problematic, since the error due to comparatoroffset and input common-mode variation of and are

both second-order-shaped in the proposed two-channel TI ar-chitecture. Fig. 8 is the simulation result that shows sensitivityto channel mismatch. The mismatch error was included in theoutput-to-input path of each quantizer.

V. CIRCUIT IMPLEMENTATION

A. Modulator

Fig. 9 shows the SC implementation of the two-channel TIsecond-order modulator. Both integrators share the inputsampling capacitors with the global feedback DAC. This alle-viates the GBW requirements of the op-amps by improving thefeedback factor of the integrators. The five-level DAC is real-ized by two capacitors whereas the three-level DAC uses onlyone capacitor. In addition, the control voltage is set to halfof the reference voltage for both DACs. This is to scalethe DAC output with the modulator input signal, since usingonly one input branch for the two-channel TI modulatoris equivalent to scaling the input signal by half (Fig. 5). Thezero-level is obtained by shorting the switches clocked withand for the five-level DAC, and for the three-level DAC.Individual level averaging (ILA) is used to shape the mismatchof the five-level DAC [16]. Furthermore, the input common-


Fig. 10. Two-stage op-amp schematic.

mode voltage of the integrators is lowered to 0.4 V, enablingthe use of small sized nMOS switches at the summing nodeof the op-amps, which can reduce the clock feedthrough mis-match. Bottom-plate sampling is used to eliminate the channelcharge injection of the remaining switches [17]. Therefore, con-trol clocks are all consistent with the delayed version of

. CMOS switches are used for control clocks , , ,and . The size of the sampling capacitors is set to 1.6 pFand 0.8 pF for the first and second integrators, considering the

noise limit.

B. Op-Amp

A two-stage op-amp is used for the first integrator due to thehigh DC gain and high output swing requirements. However,the relaxed requirements of the second integrator enable using asingle-stage op-amp. Fig. 10 shows the two-stage op-amp withcascade compensation scheme [18]. The open-loop DC gain is74 dB with GBW of 450-MHz. The op-amp for the second in-tegrator only uses the folded cascade first stage. SC common-mode feedback is used for both op-amps. The total current con-sumption to meet the noise and settling requirement is 1.3 mAfor the first integrator op-amp and 0.6 mA for the second inte-grator op-amp, both excluding the current of the bias circuits.

C. Multibit Quantizer

A flash ADC which includes the poly-Si resistor ladder, com-parator, and SR-latch is used for each quantizer. Fig. 11 showsthe comparator. The dynamic regenerative latch is used for high-speed operation and kick-back noise reduction [19]. The outputof the comparator is latched 2 ns after the rising edge of byCLK, where is the sampling phase and is the integrationphase of the integrators. With pre-amplifier gain of 14.5 dB andbias current of 30 A, the worst case conversion time for thefive-level quantizer is 1.8 ns.

VI. EXPERIMENTAL RESULTS

Fig. 12 shows the chip micrograph. The circuit is imple-mented using 0.18- m CMOS technology with 1-poly and

Fig. 11. Comparator schematic.

Fig. 12. Chip micrograph.

Fig. 13. Off-chip reference voltage generator.

5-metal layers. The core area is 1.1 mm . The referencevoltages and are generated off-chip using discretecomponents as shown in Fig. 13.

Fig. 14 shows the measured output spectrum with 6-dBFS,201.45-kHz sine-wave input. With the fundamental tone, an ad-ditional input alias is observed at . This is dueto the down-sampling effect of the input, since, as shown in(10a) and (10b), the input signal term is only included in thesecond modulator output . However, this is not problematicsince it does not overload the quantizers and can be removedby the following low-pass-filter stages. Fig. 15 is the measuredoutput spectrum with shorted inputs. In this case, idle tones areshown in the high-frequency range. However, these tones arecompletely removed by applying an input with amplitude largerthan 60 dBFS. Fig. 16 shows the SNR and SNDR versus theinput amplitude with input signal frequency of 201.45 kHz. TheSNR and SNDR is obtained by summing the noise and noiseplus harmonic tones, respectively up to the modulator signalbandwidth of 1.1 MHz. Therefore, the major harmonic tones(second, third, fourth, and fifth) of the modulator output are all


Fig. 14. Measured output spectrum with �6-dBFS input.

Fig. 15. Measured output spectrum with shorted inputs.

included in the SNDR calculation. The peak SNR and SNDRare 80 and 76 dB, with dynamic range of 85 dB. Table II showsthe performance of the proposed two-channel TI modulator.The internal blocks operate at 66 MHz with a 1.8-V supply, re-sulting in the effective sampling rate of 132 MHz. Therefore, asignal bandwidth of 1.1 MHz can be achieved with .The power consumption of the analog and digital circuits ex-cluding the off-chip reference generator is 4.2 and 1.2 mW, re-spectively. The power consumption of each subblock is shownin Table III.

The performance of the two-channel TI modulator iscompared with recently published discrete-time modulatorsfor broadband applications which have signal bandwidth largerthan 1 MHz and resolution higher than 13 b. Table IV showsthe comparison results. In order to make the comparison on thesame basis, the power consumption for each case includes onlythe modulator power, excluding the power consumption ofthe reference generators. The figure of merit (FoM) of eachmodulator is obtained by [20]

FoMPower

SNDR(15)

Fig. 16. Measured SNR and SNDR versus input amplitude.

TABLE IIMODULATOR PERFORMANCE

The FoM of the proposed modulator is competitive com-pared with other modulators. This is mainly due to thelow-power consumption obtained by the simplified two-channelTI architecture using only two op-amps.

VII. CONCLUSION

In this paper, a two-channel TI second-order modulatoris presented. The proposed two-channel TI architecture reducesthe design complexity compared with conventional TI mod-ulators, while minimizing the performance degradation due tosome simplifications. Furthermore, the proposed modulatoris robust to channel-mismatch effects, which is a key limita-tion of multichannel TI modulators that must be heeded.A two-stage op-amp with high DC gain is used for the first in-tegrator to compensate for the degradation caused by the phaseerror of the integrator. Finally, this study shows the feasibilityof obtaining power and area efficiency by using the TItechnique.


TABLE IIIPOWER CONSUMPTION OF EACH SUBBLOCK

TABLE IVPERFORMANCE COMPARISON WITH BROADBAND �� MODULATORS

ACKNOWLEDGMENT

The authors would like to thank J. Koh, Texas InstrumentsInc., for helpful comments and reviewing the manuscript.

REFERENCES

[1] T.-H. Kuo, K.-D. Chen, and H.-R. Yeng, “A wideband CMOS sigma-delta modulator with incremental data weighted averaging,” IEEE J.Solid-State Circuits, vol. 37, no. 1, pp. 11–17, Jan. 2002.

[2] R. Reutemann, P. Balmelli, and Q. Huang, “A 33 mW 14b 2.5MSample/s �� A/D converter in 0.25 �m digital CMOS,” in IEEEISSCC Dig. Tech. Papers, 2002, vol. 45, pp. 316–317.

[3] S. K. Gupta and V. Fong, “A 64-MHz clock-rate��ADC with 88-dBSNDR and �105-dB IM3 distortion at a 1.5 MHz signal frequency,”IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1653–1661, Dec. 2002.

[4] R. Jiang and T. S. Fiez, “A 14-bit�� ADC with 8� OSR and 4-MHzconversion bandwidth in a 0.18 um CMOS process,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 63–74, Jan. 2004.

[5] R. del Rio et al., “Highly linear 2.5-V CMOS �� modulator forADSL+,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp.47–62, Jan. 2004.

[6] R. Gaggl, M. Inversi, and A. Wiesbauer, “A power optimized 14-bitSC �� modulator for ADSL CO applications,” in IEEE ISSCC Dig.Tech. Papers, 2004, vol. 47, pp. 82–83.

[7] K.-Y. Nam, S.-M. Lee, D. K. Su, and B. A. Wooley, “A low-voltagelow-power sigma-delta modulator for broadband analog-to-digital con-version,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1855–1864,Sep. 2005.

[8] P. Balmelli and Q. Huang, “A 25 MS/s 14-b 200-mW �� modulatorin 0.18 �m CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp.2161–2169, Dec. 2004.

[9] R. K. Poorfard, L. B. Lim, and D. A. Johns, “Time-interleaved over-sampling A/D converters: Theory and practice,” IEEE Trans. CircuitsSyst. II, Analog Digit. Signal Process., vol. 44, no. 8, pp. 634–645, Aug.1997.

[10] M. Kozak and I. Kale, “Novel topologies for time-interleaved delta-sigma modulators,” IEEE Trans. Circuits Syst. II, Analog Digit. SignalProcess., vol. 47, no. 7, pp. 639–654, Jul. 2000.

[11] K. Lee and F. Maloberti, “Time-interleaved sigma-delta modulatorusing output prediction scheme,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 51, no. 10, pp. 537–541, Oct. 2004.

[12] L. Sumanen, M. Waltari, and K. Halonen, “A 10-bit 200-MS/s CMOSpipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 36, no. 7,pp. 1048–1055, Jul. 2000.

[13] K. Lee, Y. Choi, and F. Maloberti, “Domino free 4-path time-inter-leaved second order sigma-delta modulator,” in Proc. IEEE Int. Symp.Circuits Syst., May 2004, vol. 1, pp. 473–476.

[14] P. Vaidyanathan, “Multirate digital filters, filter banks, polyphase net-works, and applications: A tutorial,” Proc. IEEE, vol. 78, no. 1, pp.56–93, Jan. 1990.

[15] P. Malcovati et al., “Behavioral modeling of switched-capacitor sigma-delta modulators,” IEEE Trans. Circuits Syst. I, Fundam. Appl. Theory,vol. 50, no. 3, pp. 352–364, Mar. 2003.

[16] F. Chen and B. H. Leung, “A high resolution multibit sigma-delta mod-ulator with individual level averaging,” IEEE J. Solid-State Circuits,vol. 30, no. 4, pp. 453–459, Apr. 1995.

[17] I. Fujimori et al., “A 90-dB SNR 2.5 MHz output rate ADC using cas-caded multibit delta-sigma modulation at 8� oversampling rate,” IEEEJ. Solid-State Circuits, vol. 35, no. 12, pp. 1820–1827, Dec. 2000.

[18] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s pipelineanalog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no.5, pp. 599–606, May 1999.

[19] S. Rabii and B. A. Wooley, “A 1.8 V digital audio sigma-delta modu-lator in 0.18 �m CMOS,” IEEE J. Solid-State Circuits, vol. 32, no. 6,pp. 783–796, Jun. 1997.

[20] C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner, “A 6-bit1.2 GS/s low-power flash-ADC in 0.13 �m digital CMOS,” IEEE J.Solid-State Circuits, vol. 40, no. 7, pp. 1499–1505, Jul. 2005.

Kye-Shin Lee (S’02–M’06) received the B.S. degreefrom Korea University, Seoul, Korea, in 1992, theM.S. degree from Texas A&M University, CollegeStation, in 2002, and the Ph.D. degree from the Uni-versity of Texas at Dallas, Richardson, TX, in 2005,all in electrical engineering.

He was with LG Semicon Company (nowHyundai Electronics) from 1994 to 1999, where hewas involved with mixed-signal circuit design andtesting of BW/color CCD chipsets, USB cameras,and sigma-delta CODECs for audio and voice appli-

cations. He is now with Texas Instruments Inc., Dallas, where he is involvedwith sigma-delta ADCs for wireless handsets. His research has been focusedon switched-capacitor circuits, continuous-time and discrete-time sigma-deltamodulators, and modeling/characterization of ADCs and DACs.


Sunwoo Kwon (S’02) received the B.E. degreefrom Korea University, Seoul, Korea, in 2000,and the M.S. degree from University of Texas atDallas, Richardson, TX, in 2004, both in electricalengineering. He is currently working towards thePh.D. degree in electrical engineering at OregonState University, Corvallis.

His research interests are high-speed low-power�� modulators and pipeline ADCs for communica-tion systems.

Franco Maloberti (SM’87–F’96) received theLaurea degree in physics (summa cum laude) fromthe University of Parma, Parma, Italy, in 1968,and the Doctorate Honoris Causa in electronicsfrom the Instituto Nacional de Astrofisica, OpticayElectronica (Inaoe), Puebla, Mexico, in 1996.

He was a Visiting Professor with the SwissFederal Institute of Technology (ETH-PEL), Zurich,Switzerland, and with the EPFL, Lausanne, Switzer-land. He was the TI/J. Kilby Chair Professor at TexasA&M University, College Station, and the Distin-

guished Microelectronic Chair Professor at the University of Texas at Dallas,Richardson. Presently, he is a Professor of Microelectronics and Head of theMicro Integrated Systems Group, University of Pavia, Italy. His professionalexpertise is in the design, analysis, and characterization of integrated circuitsand analog digital applications, mainly in the areas of switched-capacitorcircuits, data converters, interfaces for telecommunication and sensor systems,and CAD for analog and mixed A/D design. He has authored or coauthoredmore than 340 published papers and four books and holds 24 patents.

Dr. Maloberti was the recipient of the XII Pedriali Prize for his technical andscientific contributions to national industrial production, in 1992. He was core-cipient of the 1996 Institute of Electrical Engineers Fleming Premium. He wasthe President of the IEEE Sensor Council from 2002 to 2003 and Vice Presi-dent, Region 8, of the IEEE Circuits and Systems (CAS) Society from 1995 to1997 and an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS II. Presently, he is serving as Vice President of Publications of theIEEE CAS Society. He was the recipient of the 1999 IEEE CAS Society Mer-itorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the2000 IEEE Millennium Medal.

Documents

K.#S. Lee, S. Kwon, F. Maloberti: A Power(Efficient Two ...ims.unipv.it/~franco/JournalPaper/100.pdf · Manuscript received August 30, 2006; revised January 3, 2007. K.-S. Lee is